RUUwith1fetch

RUUwith1fetch - CACTI 5.3 Normal Interface Detailed...

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CACTI 5.3 Normal Interface RAM Size (bytes) Detailed Interface Nr. of Banks Pure RAM Interface Read/Write Ports FAQ Read Ports Write Ports Single Ended Read Ports Nr. of Bits Read Out Technology Node (nm) Temperature (300-400 K, steps of 10) RAM cell/transistor type in data array (choose ITRS transistor for SRAM cell) ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM COMM-DRAM Peripheral and global circuitry transistor type in data array ITRS-HP ITRS-LSTP ITRS-LOP RAM cell/transistor type in tag array (choose ITRS transistor for SRAM cell) ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM COMM-DRAM Peripheral and global circuitry transistor type in tag array ITRS-HP ITRS-LSTP ITRS-LOP Interconnect projection type Aggressive Conservative Type of wire outside mat Semi-global Global
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RAM Parameters: Number of banks:1 Total RAM Size (bytes):616 Read/Write Ports per bank:0 Read Ports per bank:8 Write Ports per bank:7 Technology Size (nm):32 Vdd:0.9 Access time (ns): 0.369819158871 Random cycle time (ns):0.156359033515 Multisubbank interleave cycle time (of data array) (ns):0.149626820244 Total read dynamic energy per read port(nJ): 0.014543207687
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RUUwith1fetch - CACTI 5.3 Normal Interface Detailed...

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