TSMC180nm

TSMC180nm - * * MOSIS WAFER ACCEPTANCE TESTS * * * RUN: T92Y

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Sheet1 Page 1 * ******************** MOSIS WAFER ACCEPTANCE TESTS ***************************** * * RUN: T92Y (MM_NON-EPI_THK-MTL) VENDOR: TSMC * TECHNOLOGY: SCN018 FEATURE SIZE: 0.18 microns * Run type: DED * * * INTRODUCTION: This report contains the lot average results obtained by MOSIS * from measurements of MOSIS test structures on each wafer of * this fabrication lot. SPICE parameters obtained from similar * measurements on a selected wafer are also attached. * * COMMENTS: DSCN6M018_TSMC * * * TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS * * MINIMUM 0.27/0.18 * Vth 0.50 -0.49 volts * * SHORT 20.0/0.18 * Idss 572 -276 uA/um * Vth 0.52 -0.49 volts * Vpt 4.7 -5.2 volts * * WIDE 20.0/0.18 * Ids0 20.8 -15.2 pA/um * * LARGE 50/50 * Vth 0.42 -0.41 volts * Vjbkd 3.7 -4.4 volts * Ijlk <50.0 <50.0 pA * * K'= Uo*Cox 342.0 -74.0 uA/V^2 * Low-field Mobility (Uo) 406.07 87.86 cm^2/V*s * * COMMENTS: Poly bias varies with design technology. To account for mask * bias use the appropriate value for the parameters XL and XW * in your SPICE model card. * * Design Technology XL (um) XW (um) * ------------------------- ------- ------ * SCN6M_DEEP (lambda=0.09) 0.00 -0.01 * thick oxide 0.00 -0.01 * SCN6M_SUBM (lambda=0.10) -0.02 0.00 * thick oxide -0.02 0.00 * * * FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS * Vth Poly >6.6 <-6.6 volts *
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Sheet1 Page 2 * * PROCESS PARAMETERS N+ P+ POLY N+BLK PLY+BLK M1 M2 UNITS * Sheet Resistance 7.0 8.1 8.3 59.5 306.6 0.08 0.08 ohms/sq * Contact Resistance 8.3 8.8 8.1 4.83 ohms * Gate Oxide Thickness 41 angstrom * * PROCESS PARAMETERS M3 POLY_HRI M4 M5 M6 N_W
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TSMC180nm - * * MOSIS WAFER ACCEPTANCE TESTS * * * RUN: T92Y

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