Virag_parekh_EE557_Project1

Virag_parekh_EE557_Project1 - EE 557 Computer Architecture...

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Unformatted text preview: EE 557 Computer Architecture Organization Project 1 Submitted by Virag Parekh II. Estimation results given by CACTI with corresponding inputs: Machine Width RUU Access time (ns) L1 data access time (ns) L1 instruction access time (ns) L2 unified access time (ns) 1 0.369819158871 0.710577835703 0.384814376034 2.52576221006 2 0.431005775202 0.710577835703 0.384814376034 2.52576221006 4 0.537376871458 0.710577835703 0.384814376034 2.52576221006 8 0.701303244266 0.710577835703 0.384814376034 2.52576221006 RUU FETCH 1 CACTI 5.3 Normal Interface RAM Size (bytes) 616 Detailed Interface Nr. of Banks 1 Pure RAM Interface Read/Write Ports FAQ Read Ports 8 Write Ports 7 Single Ended Read Ports Nr. of Bits Read Out 152 Technology Node (nm) 32 Temperature (300-400 K, steps of 10) 360 RAM cell/transistor type in data array (choose ITRS transistor for SRAM cell) ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM COMM-DRAM Peripheral and global circuitry transistor type in data array ITRS-HP ITRS-LSTP ITRS-LOP RAM cell/transistor type in tag array (choose ITRS transistor for SRAM cell) ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM COMM-DRAM Peripheral and global circuitry transistor type in tag array ITRS-HP ITRS-LSTP ITRS-LOP Interconnect projection type Aggressive Conservative Type of wire outside mat Semi-global Global submit cache pure_sram S ubmit RAM Parameters: Number of banks:1 Total RAM Size (bytes):616 Read/Write Ports per bank:0 Read Ports per bank:8 Write Ports per bank:7 Technology Size (nm):32 Vdd:0.9 Access time (ns): 0.369819158871 Random cycle time (ns):0.156359033515 Multisubbank interleave cycle time (of data array) (ns):0.149626820244 Total read dynamic energy per read port(nJ): 0.014543207687 Total read dynamic power per read port at max freq (W): 0.093011624337 Total standby leakage power per bank (W): 0.0132183707563 Refresh power (percentage of standby leakage power): 0.0 Total area (mm^2): 0.541434877152 DRAM array refresh interval (microseconds):0.0 DRAM array availability (percentage):0.0 Best number of wordline segments: 4 Best number of bitline segments: 2 Best number of sets per wordline: 1.0 Best degree of bitline muxing: 1 Best degree of sense-amp level 1 muxing: 1 Best degree of sense-amp level 2 muxing: 2 Time Components: delay_route_to_bank (ns):0.0 addr_din_horizontal_htree (ns):0.0787413785927 addr_din_vertical_htree (ns):0.0220985401895 row_predecode_driver_and_block (ns):0.0487869014616 row_decoder (ns):0.0503897233445 bitlines (ns):0.0409283123322 sense_amp (ns):0.00254623618878 subarray_output_driver (ns):0.0475866881685 bit_mux_predecode_driver_and_block (ns):0.0 bit_mux_decoder (ns):0.0 senseamp_mux_lev_1_predecode_driver_and_block (ns):0.0 senseamp_mux_lev_1_decoder (ns):0.0 senseamp_mux_lev_2_predecode_driver_and_block (ns):0.0467001588695 senseamp_mux_lev_2_decoder (ns):0.0 delay_dout_vertical_htree (ns):0.0 delay_dout_horizontal_htree (ns):0.0787413785927 Power Components: Percentage of total dynamic power: routing_to_bank:0.0 addr_horizontal_htree:2.10607961011 addr_horizontal_htree:2....
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This note was uploaded on 08/15/2010 for the course EE 441 taught by Professor Neely during the Spring '08 term at USC.

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Virag_parekh_EE557_Project1 - EE 557 Computer Architecture...

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