virag_parekh_proj2

virag_parekh_proj2 - EE 557 Project Phase 2 Design of an...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 557 Project Phase 2 Design of an Optimum Out-of order processor using CACTI and Superscalar Submitted by Virag Parekh
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
FINAL DESIGN OF THE PROCESSOR I-fetch queue size = 2 Branch predictor type used: comb Branch prediction bimodal: 4096 Branch predictor-2lev-pag: 4096, 65536 (level1, level2) Size of branch predictor history: 16 Size of Branch predictor buffer: 4096 sets and 8-way associativity Number of Entries in BTB =4096*8 = 32768 Size of return address stack: 8 Machine Width = 4 (size of issue/decode/commit per cycle) RUU size: 64 Load/Store Queue: 64 Cache level 1- instruction: 256KB, 4-way associative Cache level 1- data: 256KB, 4-way associative Cache level 2- data: 4MB, 4way associative Reg: ALU 2 Reg: MUL 1 Reg: memport 1 Reg fpalu: 1 Reg: fpmult 1 MIPS = 2596.46 The calculation of MIPS is shown in later part of the project report. The following are the steps carried out to find the MIPS of the processor Step 1: Insert the parameters in real-estimator Step 2: Use the number of ports form real-estimator into CACTI to find the access time Step 3: Calculate the latency of caches Step 4: Simulate and use the output of simulations to calculate MIPS.
Background image of page 2
RUU, number of entries = 64 The access time of RUU with 64 entries is coming as 0.4355ns as shown below from CACTI.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
L1 instruction cache - The access time of L1 instruction cache with 256KB and 4 way associativity is coming as 0.86335ns as hown below from CACTI.
Background image of page 4
L1 data cache - The access time of L1 data cache with 256KB and 4 way associativity is coming as 0.86335ns as shown below from CACTI.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
L2 unified cache The access time of L2 unified cache with 4MB and 4 way associativity is coming as 2.73503 ns as shown below from CACTI
Background image of page 6
ACCESS TIME AND CACHE LATENCY CALCULATIONS RUU L1 data L1 instruction L2 unified Access time 0.4355 0.86335 0.86335 2.73503 Latency 1 2 2 7 Sim_cycle for twolf = 127067011 Sim_cycle for equake = 57405868 Sim_cycle for applu = 63455508 Sim_cycle for bzip2 = 96802123 Sim_cycle for gcc = 97451059 Total sim_cycle = 442181569 Total number of instructions committed = 100000000 * 5 = 500000000 MIPS = (Total number of instruction committed)/(sum of simulation cycles * clock cycle time)
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 08/15/2010 for the course EE 441 taught by Professor Neely during the Spring '08 term at USC.

Page1 / 17

virag_parekh_proj2 - EE 557 Project Phase 2 Design of an...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online