Quitoriano08

Quitoriano08 - Integratable Nanowire Transistors Nathaniel...

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Unformatted text preview: Integratable Nanowire Transistors Nathaniel J. Quitoriano* and Theodore I. Kamins* Information and Quantum Systems Laboratory, Hewlett-Packard Laboratories, Palo Alto, California 94304 Received July 29, 2008; Revised Manuscript Received October 16, 2008 ABSTRACT We report a structure to control nanowire location and growth direction and demonstrate top-gated, metal- oxide- semiconductor, field-effect transistors (MOSFETs) using this structure. The nanowires were engineered to grow against an oxide surface of a (001), silicon-on-insulator substrate, enabling straightforward fabrication of MOSFETs exhibiting an I on / I off ratio 104 and a subthreshold slope of 155 mV/decade. Though nanowires were engineered to grow in 110 directions, the nanowires still grew by the addition of {111} planes. Metal-catalyzed, self-assembled, semiconducting nanowires have been proposed as the basis for fabricating nanometer- scale electronic, optical, and sensing devices without expen- sive, fine-scale lithography. 1,2 Despite their promising prop- erties, difficulty controlling their location and integrating them prevents their widespread use. To date, most work has focused on growing the nanowires (NWs) on one substrate, removing them, then placing them on another substrate to connect them to electrodes, making integration difficult. 3- 5 Alternatively, NWs can be grown in locations where devices can be fabricated. Nanowires can be grown vertically on (111) substrates 6,7 or horizontally above a surface to bridge between two electrodes; 8,9 however, processing the resulting nonplanar structures is difficult. Here we report a structure enabling control of nanowire location and growth direction, which we use to demonstrate top-gated, metal-oxide- semiconductor, field-effect transistors (MOSFETs) patterned using conventional planar technology. The nanowires were engineered to grow in crystallographic directions against the surface of the buried oxide (BOX) layer of a (100)-oriented, silicon-on-insulator (SOI) substrate. Trenches were cut into the top Si layer of the SOI substrate. Some of the buried oxide layer was etched isotropically, undercutting the top Si layer. Nanowires were selectively nucleated from this undercut region and grew against the oxide in a 110 -type direction. These nanowires bridged between two Si regions subsequently used as the source and drain electrodes of the MOSFET, which exhibited an I on / I off ratio 104 and an inverse subthreshold slope of 155 mV/decade. Growing nanowires in contact with the surface in a predefined location makes the nanowires more robust to further processing and can enable the integration of multiple nanowire devices. This integration can help realize the full promise of semiconduct- ing nanowires since practical applications of nanowire devices are likely to use a combination of top-down patterning with self-assembly to integrate nanowires with conventionally formed structures....
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Quitoriano08 - Integratable Nanowire Transistors Nathaniel...

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