Zhang08

Zhang08 - IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55,...

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 11, NOVEMBER 2008 2907 An Analytic Model for Nanowire MOSFETs With Ge/Si Core/Shell Structure Lining Zhang, Jin He, Member, IEEE , Jian Zhang, Feng Liu, Yue Fu, Yan Song, and Xing Zhang Abstract —An analytic model for the nanowire MOSFETs (NWFETs) with Ge/Si core/shell structure is developed in this paper. The analytical expressions of electrostatic potential and charges of this device are derived from classical device physics under the gradual channel approximation. Then, a drift-diffusion (DD) mechanism-based drain current model is obtained and veri±ed by comparisons with the numerical simulation results. By modifying the intrinsic carrier concentration under 2-D con- ±nement, quantum–mechanical effect is also taken into account approximately, and then, a ballistic current model is developed to study the impact of quantum–mechanical effect on the device characteristics. The performances of Ge/Si core/shell NWFETs are analyzed, and signi±cant characteristics are demonstrated, in detail, by the proposed model. The presented analytic model may provide a base for device scientists and circuit engineers to understand the device physics and further develop a compact model of the NWFETs with Ge/Si core/shell heterostructure for circuit design and simulation. Index Terms —Analytic model, ballistic transport, core/shell, Ge/Si heterojunction, nanowire MOSFETs (NWFETs), Poisson–Boltzmann equation, quantum–mechanical effect. I. INTRODUCTION A CCORDING to the updated international technology roadmap for semiconductors, the traditional bulk CMOS structure will soon hit its limit due to severe short-channel effect and gate tunneling [1]. To extend the scalability of CMOS technology into or beyond the 32-nm generation node, some nonclassical new device structures such as double-gate [2], surrounding-gate (SRG) [3], and nanowire [4] MOSFETs have been proposed. Among them, nanowire devices are considered the best ones for their strongest gate control to the channel and high integration density [4], [5]. Manuscript received May 22, 2008; revised July 21, 2008. Current version published October 30, 2008. This work was supported in part by the Special Funds for Major State Basic Research Project (973), and by the National Natural Science Foundation of China under Grant 60876027. The review of this paper was arranged by Editor M. Meyyappan. L. Zhang, J. He, and X. Zhang are with the TSRC, Key Laboratory of Microelectronic Devices and Circuits, Ministry of Education, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871, China and also with Group of Micro- & Nano- Electronic Device and Integrated Technology, The Key Laboratory of Integrated Microsys- tems, Peking University Shenzhen Graduate School, Shenzhen 518055, China (e-mail: frankhe@pku.edu.cn).
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Zhang08 - IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55,...

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