Simulation Tutorial_ VHDL D. - Active-HDL Simulation...

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Unformatted text preview: Active-HDL Simulation Introduction: 1-bit Full Adder VHDL Design & Simulation I. Introduction In this lab the functionality of a design, in our case a 1-bit adder, is written in a VHDL. The correctness of the design is verified at the software level through simulation, thus saving critical design time. II. Procedure Creating the 1-bit adder Start ALDEC Active-HDL 1. Select "Create New Design" and click OK 2. Enter adder1 as the name of the project and change the directory to c:\lab1 and click NEXT 3. Select "Create Empty Design" and click NEXT 4. Click FINISH 5. Double-click on "Add New File" in the Design Browser window 6. Select "VHDL Source Code" and type in adder1 in the name field, click OK. 7. The following is the VHDL code for the 1-bit adder. Enter the code as seen below into the empty file. 8. NOTE: All lines that start with "--" are not needed. These are comments to help you better understand what the actual code is doing.-- We declare the 1-bit adder with the inputs and outputs-- shown inside the port().-- This will add two bits together(x,y), with a carry in(cin) and -- output the sum(sum) and a carry out(cout). entity BIT_ADDER is port ( a, b, cin : in bit; sum, cout : out bit ); end entity BIT_ADDER;-- This describes the functionality of the 1-BIT adder. architecture BHV of BIT_ADDER is begin -- Calculate the sum of the 1-BIT adder....
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Simulation Tutorial_ VHDL D. - Active-HDL Simulation...

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