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# VHDLh - Acknowledgment DLD Lab Introduction to VHDL(Very...

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DLD Lab Introduction to VHDL ( V ery H igh Speed Integrated Circuit Hardware D escription L anguage) Acknowledgment This set of slides on VHDL are due to Brown and Vranesic. A simple logic function and corresponding VHDL code f x 3 x 1 x 2 VHDL code for a four-input function f g x 3 x 1 x 2 x 4 Logic circuit for four-input function Figure 6.27 VHDL code for a 2-to-1 multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN WITH s SELECT f <= w0 WHEN '0', w1 WHEN OTHERS ; END Behavior ;

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Figure 6.1 A 2-to-1 multiplexer (a) Graphical symbol f s w 0 w 1 0 1 (b) Truth table 0 1 f f s w 0 w 1 (c) Sum-of-products circuit s w 0 w 1 (d) Circuit with transmission gates w 0 w 1 f s LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Behavior ; Figure 6.28 VHDL code for a 4-to-1 multiplexer Figure 6.2 A 4-to-1 multiplexer f s 1 w 0 w 1 00 01 (b) Truth table w 0 w 1 s 0 w 2 w 3 10 11 0 0 1 1 1 0 1 f s 1 0 s 0 w 2 w 3 f (c) Circuit s 1 w 0 w 1 s 0 w 2 w 3 (a) Graphic symbol Figure 6.28 Component declaration for the 4-to-1 multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE mux4to1_package IS COMPONENT mux4to1 PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END COMPONENT ; END mux4to1_package ; Figure 6.3 Using 2-to-1 multiplexers to build a 4-to-1 multiplexer 0 w 0 w 1 0 1 w 2 w 3 0 1 f 0 1 s 1 s Figure 6.29 Hierarchical code for a 16-to-1 multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY work ; USE work.mux4to1_package.all ; ENTITY mux16to1 IS PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux16to1 ; ARCHITECTURE Structure OF mux16to1 IS
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