Homework 3 Solutions - Part I

Homework 3 Solutions - Part I - Modern Processor Design:...

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Modern Processor Design: Fundamentals of Superscalar Processors 10 This instruction performs two register writes. It can either be underpipelined, by forcing the sec- ond write to stall the pipeline, or, to maintain a fully pipelined implementation, a second write port must be added to the register file. In addition, the hazard detection and bypass network must be augmented to handle this special case of a second register write. 10. Given the change outlined in Problem 9, redraw the pipeline interlock hardware shown in Figure 2-20 to correctly handle the load-update instruction. The figure should be modified to include the changes described above. 11. Bypass network design: given the following ID, EX, MEM, and WB pipeline configuration, draw all necessary Mux0 and Mux1 bypass paths to resolve RAW data hazards. Assume that load instructions are always separated by at least one independent instruction (possibly a NOP) from any instruction that reads the loaded register (hence you never stall due to a RAW hazard). 12. Given the forwarding paths in Problem 11, draw a detailed design for Mux0 and Mux1 that
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Homework 3 Solutions - Part I - Modern Processor Design:...

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