Homework 3 Solutions - Part I

Homework 3 Solutions - Part I - Modern Processor Design...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Modern Processor Design: Fundamentals of Superscalar Processors 10 This instruction performs two register writes. It can either be underpipelined, by forcing the sec- ond write to stall the pipeline, or, to maintain a fully pipelined implementation, a second write port must be added to the register file. In addition, the hazard detection and bypass network must be augmented to handle this special case of a second register write. 10. Given the change outlined in Problem 9, redraw the pipeline interlock hardware shown in Figure 2-20 to correctly handle the load-update instruction. The figure should be modified to include the changes described above. 11. Bypass network design: given the following ID, EX, MEM, and WB pipeline configuration, draw all necessary Mux0 and Mux1 bypass paths to resolve RAW data hazards. Assume that load instructions are always separated by at least one independent instruction (possibly a NOP) from any instruction that reads the loaded register (hence you never stall due to a RAW hazard). 12. Given the forwarding paths in Problem 11, draw a detailed design for Mux0 and Mux1 that
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 08/22/2010 for the course CDA 5106 taught by Professor Staff during the Spring '08 term at University of Central Florida.

Page1 / 2

Homework 3 Solutions - Part I - Modern Processor Design...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online