final_review - University of Central Florida CDA 5106 5106...

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1 University of Central Florida CDA 5106 Review Prof. Mark Heinrich School of Electrical Engineering and Computer Science heinrich@eecs.ucf.edu ± You learned alot! • Historical trends, performance, and power • Quantitative performance and cost analysis Congratulate Yourself • Architectural simulation • Advanced pipelining • High-performance microarchitecture • Dynamic branch prediction • HW speculation, out-of-order execution, RATs • Memory Hierarchy, Virtual Memory, and Advanced Caching Techniques Prefetching Mul -threading Predication and mul -core processor UCF • Prefetching, Multi threading, Predication, and multi core processors • Current industry processors ± No one knows what is next in computer architecture • Exciting time for research
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2 ± Do instruction sets matter? • RISC vendors are disappearing • No major performance difference between RISC and CISC RISC vs. CISC • Most 3 rd party software runs on CISC architectures – x86, IBM 360 ± But, RISC is much easier to implement • Possibly reach higher clock rates with less effort • HW can translate CISC input to RISC implementation UCF ± So, do instruction sets matter? • Yes, there must be a standard instruction set to sell machines! 4 Instruction Fetch (IF) Decode (RD) Execute (EX) Memory (MEM) Writeback (WB) A Pipelined Datapath pc imem dmem regs alu + IR =? lmd UCF e x t e n d 16 32 smd
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3 ± Longer pipes and multi-cycle ALU ops create more problems • Stalls even in the face of full bypassing P i ti i f f d l t i Advanced Pipelining ± Precise exceptions in face of out-of-order completion ± WAW hazards ± More branch/load delay slots?
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final_review - University of Central Florida CDA 5106 5106...

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