Lecture 5 - Memory Hierarchy (2010-01-26)

Lecture 5 Memory - Chapter 3 Memory and I/O Systems Modern Processor Design Fundamentals of Superscalar Processors Computer Science Department

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Chapter 3: Memory and I/O Systems Modern Processor Design: Fundamentals of Superscalar Processors Computer Science Department University of Central Florida Memory Hierarchy • “Anyone can build a fast CPU. The trick is to build a fast system.” – Seymour Cray • Memory Memory – Just an “ocean of bits” – Many technologies are available • Key issues – Technology (how bits are stored) – Placement (where bits are stored) – Identification (finding the right bits) 2 – Replacement (finding space for new bits) – Write policy (propagating changes to bits) • Must answer these regardless of memory type
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Types of Memory Type Size Speed Cost/bit Register < 1KB < 1ns $$$$ On-chip SRAM 8KB-6MB < 10ns $$$ Off-chip SRAM 1Mb – 16Mb < 20ns $$ DRAM 64MB – 1TB < 100n $ 3 < 100ns Disk 40GB – 1PB < 20ms ~0 Memory Hierarchy Registers On-Chip SRAM Off-Chip SRAM CAPACITY ED and COST 4 DRAM Disk SPE
Background image of page 2
3 Why Memory Hierarchy? • Need lots of bandwidth Gcycles Df B i Dref If t h B i Ifetch l inst BW 2 4 4 . 0 4 1 0 . 1 × × + × × = – Implication: ultra fast access and/or a high number of bits per access • Need lots of storage – 64MB (minimum) to multiple TB Must be cheap per bit s GB s Dref inst Ifetch inst cycle 2 . 11 = 5 – (TB x anything) is a lot of money! • These requirements seem incompatible Why Memory Hierarchy? • Fast and small memories – Enable quick access (fast cycle time) – Enable lots of bandwidth (1+ L/S/ fetch/cycle – Enable lots of bandwidth (1+ L/S/I-fetch/cycle) • Slower larger memories – Capture larger share of memory – Still relatively fast • Slow huge memories – Hold rarely-needed state – Needed for correctness 6 Needed for correctness • All together: provide appearance of large, fast memory with cost of cheap, slow memory – This illusion CAN be broken! – “Virtual memory leads to virtual performance” – Seymour Cray (He also believed this about memory hierarchies)
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 Why Does a Hierarchy Work? • Locality of reference – Temporal locality • Reference same memory location repeatedly Reference same memory location repeatedly – Spatial locality • Reference near neighbors around the same time • Empirically observed – Significant! – Even small local storage (8KB) often satisfies >90% of references to multi-MB data set 7 Memory Hierarchy CPU Temporal Locality •Keep recently referenced items at higher levels Spatial Locality •Bring neighbors of recently referenced to higher levels I & D L1 Cache Shared L2 Cache •Future references satisfied quickly •Future references satisfied quickly 8 Main Memory Disk
Background image of page 4
5 Four Burning Questions • These are: –P l a c em e n t • Where can a block of memory go Where can a block of memory go? – Identification • How do I find a block of memory?
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 08/22/2010 for the course CDA 5106 taught by Professor Staff during the Spring '08 term at University of Central Florida.

Page1 / 44

Lecture 5 Memory - Chapter 3 Memory and I/O Systems Modern Processor Design Fundamentals of Superscalar Processors Computer Science Department

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online