Lecture 13 - Pipelining (2010-02-23)

Lecture 13 - Pipelining (2010-02-23) - CDA 5106 Advanced...

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1 CDA 5106 Advanced Computer Architecture I Pipelining Computer Science Department University of Central Florida Designing a processor • Design the ISA • Classify instructions for the ISA (e.g., MIPS): Memory reference – Memory references – Register-Register ALU Operations – Register-Immediate ALU Operations – Branches • Work out the execution for each operation class • Design appropriate hardware • Look for opportunities to improve 2 • Look for opportunities to improve… • …while maintaining correct execution
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2 How to Execute an Instruction • Instruction fetch (“IF”) –I R = M em [ P C ] – NPC = PC + 4 Instruction decode/Register fetch (“ID” Instruction decode/Register fetch ( ID ) –A = R e g s [ I R 6..10 ] –B = R e g s [ I R 11. .15 ] – Imm = sign-extend(IR 16. .31 ) •E x e c u t e ( E X ) – Memory reference: • ALUOutput = A + Imm – Reg/Reg ALU Operation: • ALUOutput = A op B 3 ALUOutput A – Reg/Immediate ALU Operation: • ALUOutput = A op Imm – Branch: • ALUOutput = NPC + Imm; Cond = (A op 0) Executing an Instruction (cont.) • Memory Access/Branch completion (“MEM“) – Memory Reference: • Load Mem Data = Mem[ALUOutput] /* Load */ Load_Mem_Data Mem[ALUOutput] / Load / • Mem[ALUOutput] = B /* Store */ r a n c h • If (cond) PC = ALUOutput, else PC = NPC •W r i t e b a c k ( “W B ) – Reg-Reg ALU Operation: •Regs[IR 16 20 ] = ALUOutput 4 16. .20 – Reg-Immediate ALU Operation: 11. .15 ] = ALUOutput – Load instruction: 11. .15 ] = Load_Mem_Data
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3 How to Execute an Instruction • Instruction fetch (“IF”) –IR = M em [ PC ] NPC = PC + 4 – NPC = PC + 4 ALU PC NPC 4 5 Instruction cache IR (inst. reg.) How to Execute an Instruction (cont.) • Instruction decode/Register fetch (“ID”) –A = R e g s [ IR 6..10 ] B = Regs[IR – B = Regs[IR 11. .15 ] – Imm = sign-extend(IR 16. .31 ) Regs A B IR (inst. reg.) 6 sign extend Imm
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4 How to Execute an Instruction (cont.) •E x e c u t e ( E X ) – Memory reference: • ALUOutput = A + Imm – Reg/Reg ALU Operation: =0? cond NPC • ALUOutput = A op B – Reg/Immediate ALU Operation: •ALUOu tpu t = A op Imm – Branch: • ALUOutput = NPC + Imm; Cond = (A op 0) A B ALU MUX 7 Imm How to Execute an Instruction (cont.) • Memory Access/Branch completion (“MEM“) – Memory Reference: UX NPC • Load_Mem_Data = Mem[ALUOutput] /* Load */ • Mem[ALUOutput] = B /* Store */ –B r a n c h • If (cond) PC = ALUOutput, else PC = NPC cond M data cache LMD PC 8
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5 How to Execute an Instruction (cont.) • Write back (“WB”) – Reg-Reg ALU Operation: •R eg s [ IR 16. .20 ] = ALUOutput –R eg-Immediate ALU Operation: s [ 11. .15 ] = ALUOutput – Load instruction: s [ 11. .15 ] = Load_Mem_Data Regs LMD MUX 9 ALU NPC =0? cond 4 Instruction Fetch (IF) Instruction Decode (ID) Execute (EX) Memory (MEM) Writeback (WB) A Instruction cache PC IR (inst. reg.) Regs A B data cache LMD 10 sign extend Imm
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6 An Abstract View of Single An Abstract View of Single-Cycle Implementation Cycle Implementation 11 Controller 12
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7 Analysis • Single-cycle Implementation -> Multi-cycle Implementation • All instructions (except branch): – IF, ID, EX, MEM, WB Branch: (12%) – IF, ID, EX, MEM • CPI = 5*0.88+4*0.12 = 4.88 cycles • Graphically: IC
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Lecture 13 - Pipelining (2010-02-23) - CDA 5106 Advanced...

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