Lecture 20 - Superscalar Organization (2010-03-25)

Lecture 20 - Superscalar Organization (2010-03-25) -...

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1 Chapter 4: Superscalar Organization Modern Processor Design: Fundamentals of Superscalar Processors School of Electrical Engineering and Computer Science University of Central Florida Limitations of Scalar Pipelines • Scalar upper bound on throughput – IPC <= 1 or CPI >= 1 • Inefficient unified pipeline – Long latency for each instruction • Rigid pipeline stall policy – One stalled instruction stalls all newer instructions 3
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2 Parallel pipelines • No unused resource in simple pipeline when CPI = 1. • To execute multiple instructions in parallel, more resource MEM IF ID EX WB MEM IF ID EX WB MEM IF ID EX WB CPI = 1 MEM IF ID EX WB MEM IF ID EX WB IPC = 2 4 MEM IF ID EX WB MEM IF ID EX WB Parallel Pipelines (a) No Parallelism (b) Temporal Parallelism (d) Parallel Pipeline Parallel Pipelines 5 (c) Spatial Parallelism
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3 • Compiler forms long issue packets of n instructions • HW need not check for dependences either disallowed within packe VLIW Processors – either disallowed within packet – or must be explicitly marked when present • Each instruction feeds into a separate ALU (can be specialized) • Register file has 2 × n read and n write ports REGISTER FILE VLIW: Pros and Cons •P r o s – no (or trivial) dependence checking – simple issue logic – simple datapath: just ALUs and a register file – potentially exploits large amounts of ILP (high IPC) •C o n s – heavily reliant on compiler ability to schedule code • sometimes poor code density (many inserted NOPs) –lockstep execution (sensitive to asynchrony, e.g., caches
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Lecture 20 - Superscalar Organization (2010-03-25) -...

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