Lecture 23 - Scalable Complexity-Effective Design (2010-04-06)

Lecture 23 - Scalable Complexity-Effective Design (2010-04-06)

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1 Scalable, Complexity Effective Design School of Electrical Engineering and Computer Science University of Central Florida Checkpoint processing and recovery • H. Akkary, R. . Rajwar and S. Srinivasan, MICRO 36, 2003 Motivation – Memory wall problem – Scalable instruction window – Constrains for scalable instruction window • ROB, RF, Shadow maps, Issue queue, LSQ • In-order retirement at a coarse grain Ch k i t ti i d University of Central Florida 2 Checkpoints retire in-order – Register–flow Instructions retire out-of-order between checkpoints – Memory-flow instructions (stores) are buffered and retired in order at the time checkpoints retire – Skipping intermediate results
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2 Checkpoint processing Instruction stream Checkpoints 1 2 3 4 oldest youngest University of Central Florida 3 CPR (cont.) Instruction stream Checkpoints 1 2 3 4 oldest youngest University of Central Florida 4 r1<= ….. r3<= …. r1<= r5<=
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3 CPR (cont.) • When exception happens Instruction stream Checkpoints 1 2 3 4 oldest youngest University of Central Florida 5 exception Checkpoints retire in-order, ck1, ck2, ck3 Then, exception happens => starting from ck3, in-order retirement at instruction level Another look at resources • Critical resources (due to their complexity, latency, power) limit the scalability of instruction window – Issue queue Issue queue – Register file – Load/store queue – ROB (removed) – Number of shadow maps (next) University of Central Florida 6
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4 OOO without ROB Buffer (resv. stations) FU1 Dispatch Fetch Issue Execute Write Back IF D E C O D E R E N A M E FU2 FUn University of Central Florida 7 I$ RF & Map Table D$ OOO with CPR Buffer (resv. stations) FU1 Dispatch
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Lecture 23 - Scalable Complexity-Effective Design (2010-04-06)

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