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Unformatted text preview: ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ To maintain cache inclusion: 1) Whenever a line enters the level‐1 cache (DL1), it must also be placed in the level‐2 cache (DL2). This has already been implemented in the original simplesim code (when there is a cache miss in DL1, the block will be retrieved from DL2, and then from memory if it is also a miss in DL2. Thus that block will be in both level‐1 and level‐2 ). 2) Whenever a line leaves the DL2 cache (is evicted due to a replacement), it must also leave DL1. This property has not been enforced in the original code. So we have to look into a function that deals with cache misses in level‐2 cache; which is cache_access(). When there is a cache miss in DL2 and a replacement block is selected, cache_access() should check if that replacement block contains any lines residing in DL1. If so, those lines have to be evicted from DL1 to maintain the inclusion property. For example, DL1 block size = 32B, DL2 block size = 128K, then a DL2 block can contain 4 DL1 blocks. Let's say we have a DL2 replacement block address = 0x00000000, it would contain DL1 blocks: 0x00000000, 0x00000020, 0x00000040, and 0x00000080 that we have to check if any of these are currently in DL1. Since there is no way to access DL1 from DL2 in the original cache_access(), one way to fix this is to add a parameter as a handle to an upper‐level cache. Then we are ready to put in the inclusion code: ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Let's repl = the selected replacement block cp = pointer to current cache level ucp = pointer to upper cache level /* **MISS** when there is a cache miss */ if (this is an access to DL2) { /* can be tested by cp or ucp value */ /* check all the possible L1 blocks that this L2 block contains */ repl_addr = CACHE_MK_BADDR(cp, repl‐>tag, set); for (counter = 0; counter < cp‐>bsize; counter += ucp‐>bsize) { /* check if this address is present in DL1 */ there = cache_probe(ucp, repl_addr+counter); if (there) /* evict from DL1 */ lat += cache_flush_addr(ucp, repl_addr+counter, now); } } ...
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  • Spring '08
  • Staff
  • cache miss, cache level  ucp, replacement block, replacement block  cp, DL2 replacement block, upper cache level

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