# 1240892459 - ComputerOrganization CDA3103 Dr.HassanForoosh

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Computer Organization CDA 3103 Dr. Hassan Foroosh  Dept. of Computer Science UCF © Copyright Hassan Foroosh 2004

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Combinational Logic  Design Case Studies General design procedure Examples Calendar subsystem BCD to 7-segment display controller Process line controller Logical function unit Arithmetic Integer representations Addition/subtraction Arithmetic/logic units
General Design Procedure for  Combinational Logic 1.  Understand the Problem What is the circuit supposed to do? Write down inputs (data, control) and outputs Draw block diagram or other picture 2.  Formulate the Problem using a Suitable Design  Representation Truth table or waveform diagram are typical May require encoding of symbolic inputs and outputs 3.  Choose Implementation Target ROM, PAL, PLA Mux, decoder and OR-gate Discrete gates 4.  Follow Implementation Procedure K-maps for two-level, multi-level Design tools and hardware description language (e.g., Verilog)

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integer number_of_days ( month, leap_year_flag) { switch (month) { case 1: return (31); case 2: if (leap_year_flag == 1) then return (29) else return (28); case 3: return (31); case 4: return (30); case 5: return (31); case 6: return (30); case 7: return (31); case 8: return (31); case 9: return (30); case 10: return (31); case 11: return (30); case 12: return (31); default: return (0); } } Calendar Subsystem Determine number of days in a month (to control watch  display) Used in controlling the display of a wrist-watch LCD screen Inputs: month, leap year flag Outputs: number of days Use software implementation to help understand the problem
leap month 28 29 30 31 month leap 28 29 30 31 0000 0001 0 0 0 1 0010 0 1 0 0 0 0010 1 0 1 0 0 0011 0 0 0 1 0100 0 0 1 0 0101 0 0 0 1 0110 0 0 1 0 0111 0 0 0 1 1000 0 0 0 1 1001 0 0 1 0 1010 0 0 0 1 1011 0 0 1 0 1100 0 0 0 1 1101 111– Formalize the Problem Encoding: Binary number for month: 4 bits 4 wires for 28, 29, 30, and 31 one-hot – only one true at any time Block diagram:

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L 28 29 30 31 0000 0001 0 0 0 1 0010 0 1 0 0 0 0010 1 0 1 0 0 0011 0 0 0 1 0100 0 0 1 0 0101 0 0 0 1 0110 0 0 1 0 0111 0 0 0 1 1000 0 0 0 1 1001 0 0 1 0 1010 0 0 0 1 1011 0 0 1 0 1100 0 0 0 1 1101 111– Choose Implementation Target and Perform Mapping Discrete gates 28 =  29 = 30 =  31 =  Can translate to S-o-P or P-o-S A’ B’ C D’ L’ A’ B’ C D’ L A’ B D’ + A D A’ D + A D’ ABCD
BCD to 7-segment display  controller Understanding the problem Input is a 4 bit bcd digit (A, B, C, D) Output is the control signals for the display (7 outputs  C0 – C6) Block diagram BCD to 7–segment control signal decoder c0  c1  c2  c3  c4  c5  c6 A   B   C   D c1 c5 c2 c4 c6 c0 c3

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A B C D C0 C1 C2 C3 C4 C5 C6 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 1 1
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## This note was uploaded on 08/22/2010 for the course CDA 3101 taught by Professor Staff during the Fall '07 term at University of Central Florida.

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1240892459 - ComputerOrganization CDA3103 Dr.HassanForoosh

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