{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

# 1882368634 - Sequential Logic Computer Organization CDA...

This preview shows pages 1–4. Sign up to view the full content.

Computer Organization CDA 3103 Dr. Hassan Foroosh Dept. of Computer Science UCF © Copyright Hassan Foroosh 2004 Sequential Logic Sequential Circuits Simple circuits with feedback Latches Edge-triggered flip-flops Timing Methodologies Cascading flip-flops for proper operation Clock skew Asynchronous Inputs Metastability and synchronization Basic Registers Shift registers C1 C2 C3 comparator value equal multiplexer reset open/closed new equal mux control clock comb. logic state Sequential Circuits Circuits with Feedback Outputs = f(inputs, past inputs, past outputs) Basis for building "memory" into logic circuits Door combination lock is an example of a sequential circuit State is memory State is an "output" and an "input" to combinational logic Combination storage elements are also memory X1 X2 Xn switching network Z1 Z2 Zn Circuits with Feedback How to control feedback? What stops values from cycling around endlessly

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
"remember" "load" "data" "stored value" "0" "1" "stored value" Simplest Circuits with Feedback Two inverters form a static memory cell Will hold value as long as it has power applied How to get a new value into the memory cell? Selectively break feedback path Load new value into cell R S Q Q' R S Q R' S' Q Q Q' S' R' Memory with Cross- coupled Gates Cross-coupled NOR gates Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) Cross-coupled NAND gates Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0) Reset Hold Set Set Reset Race R S Q \Q 100 Timing Behavior R S Q Q' S R Q 0 0 hold 0 1 0 1 0 1 1 1 unstable State Behavior of R-S latch Truth table of R-S latch behavior Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 Q Q' 1 1
Theoretical R-S Latch Behavior State Diagram States: possible values Transitions: changes based on inputs Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 Q Q' 1 1 SR=00 SR=11 SR=00 SR=10 SR=01 SR=00 SR=10 SR=00 SR=01 SR=11 SR=11 SR=10 SR=01 SR=01 SR=10 SR=11 possible oscillation between states 00 and 11 Observed R-S Latch Behavior Very difficult to observe R-S latch in the 1-1 state One of R or S usually changes first Ambiguously returns to state 0-1 or 1-0 A so-called "race condition" Or non-deterministic transition SR=00 SR=00 Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 SR=10 SR=01 SR=00 SR=10 SR=00 SR=01 SR=11 SR=11 SR=01 SR=10 SR=11 Q(t+ ) R S Q(t) S R Q(t) Q(t+ ) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 X 1 1 1 X hold reset set not allowed characteristic equation Q(t+ ) = S + R’ Q(t) R-S Latch Analysis Break feedback path R S Q Q' 0 0 1 0 X 1 X 1 R SR Q(t) 00 01 11 10 0 1 enable' S' Q' Q R' R S Gated R-S Latch Control when R and S inputs matter Otherwise, the slightest glitch on R

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 9

1882368634 - Sequential Logic Computer Organization CDA...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online