1240894545 - Division Paper and Pencil Example(unsigned 20 6 = 3 Remainder 2 00011 Quotient Dividend Computer Organization CDA 3103 Dr Hassan

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Computer Organization CDA 3103 Dr. Hassan Foroosh Dept. of Computer Science UCF © Copyright Hassan Foroosh 2004 Division: Paper and Pencil ± Example (unsigned): 20 ÷ 6 = 3 Remainder 2 00011 Quotient 110 10100 Dividend 10 101 1010 - 110_ 1000 - 110 10 Remainder ± Algorithm: ± If Partial Remainder > Divisor ± then Quotient bit = 1; Remainder = Remainder – Divisor ± else Quotient bit = 0 ± Shift down next dividend bit ± 3 versions of divide, successive refinement Divisor Division Hardware Version 1 ± 64-bit Divisor reg (divisor in upper half), 64-bit ALU, 64-bit Remainder reg(dividend in lower half), 32-bit Quotient reg. 64-bit ALU Control test Quotient Shift left Remainder Write Divisor Shift right 64 bits 64 bits 32 bits Figure 4.36 from text Division Algorithm Version 1 Takes n+1 Steps for n-bit Quotient and Remainder Takes n+1 Steps for n-bit Quotient and Remainder 2a. Quotient = Quotient <<1; Quotient ++; Done Start Done Test Remainder 2a. Shift the Quotient register to the left, setting the new rightmost bit to 1 3. Shift the Divisor register right 1 bit 33rd repetition? Start Remainder < 0 No: < 33 repetitions Yes: 33 repetitions 2b. Restore the original value by adding the Divisor register to the Remainder register and place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0 1. Subtract the Divisor register from the Remainder register and place the result in the Remainder register Remainder > 0 Figure 4.37 from text
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Division Example ± Example: 7÷3 = 2; remainder 1. Iter Step Remainder Divisor Quotient Action 0 0 000111 011000 000 Initialize 1 1 101111 011000 000 Subtract 1 2b. 000111 011000 000 Restore; shift 1 3 000111 001100 000 Shift divisor 2 1 111010 001100 000 Subtract 2 2b. 000111 001100 000 Restore; shift 2 3 000111 000110 000 Shift divisor 3 1 000001 000110 000 Subtract 3 2a. 000001 000110 001 Shift in 1 3 3 000001 000011 001 Shift divisor 4 1 111110 000011 001 Subtract 4 2b. 000001 000011 010 Restore; shift 4 3 000001 000001 010 Shift divisor Observations on Division Version 1 ± Half the bits in divisor always 0 ± Half of 64-bit adder is wasted ± Half of divisor is wasted ± Instead of shifting the divisor right, we can shift the remainder left ± The first step cannot produce a 1 in quotient bit (otherwise the quotient will be too big) ± switch order to shift first and then subtract, saves 1 iteration Division Hardware Version 2 ± 32 -bit Divisor register, 32 -bit ALU, 64-bit Remainder register, 32-bit Quotient register Control test Quotient Shift left Write 32 bits 64 bits 32 bits Shift left Divisor 32-bit ALU Remainder Figure 4.39 from text Figure 4.39 from text 2a. Quotient = Quotient <<1; Quotient ++; Done 1. Remainder = Remainder – Divisor Test Remainder Remainder < 0 Remainder >= 0 3. Remainder = Remainder << 1 32 repetitions? No Yes Start 0. Remainder = Dividend << 1; 2b. Remainder = Remainder + Divisor; Quotient <<1; Division Algorithm Version 2 Takes n Steps for n-bit Quotient and Remainder Takes n Steps for n-bit Quotient and Remainder Affects Upper Half of Remainder Affects Upper Half of Remainder
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Observations on Division Version 2 ± Remainder register loses a bit every cycle; quotient gains a bit every cycle.
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This note was uploaded on 08/22/2010 for the course CDA 3101 taught by Professor Staff during the Fall '07 term at University of Central Florida.

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1240894545 - Division Paper and Pencil Example(unsigned 20 6 = 3 Remainder 2 00011 Quotient Dividend Computer Organization CDA 3103 Dr Hassan

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