1773238865 - Computer System Organization Computer...

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Computer Organization CDA 3103 Dr. Hassan Foroosh Dept. of Computer Science UCF © Copyright Hassan Foroosh 2004 Computer System Organization Processor Computer Control Datapath Memory Devices Input Output Cover control and datapath design Cover control and datapath design Emphasize control structure Use previous ALU design in datapath Use previous ALU design in datapath Single-Cycle Implementation Outline ± The Big Picture ± MIPS ISA Subset ± Clocking Methodology ± Datapath Components ± Single-Cycle Design ± Assembling the Datapath ± Controlling the machine ± Advantages and Disadvantages Performance Impact ± Performance of a machine is determined by ± Instruction count ± Clock cycle time ± Clock cycles per instruction ± Processor design (datapath and control) determines ± Clock cycle time ± Clock cycles per instruction (for a fixed instruction mix) ± In this part: Single-cycle processor ± Advantage ± Only one clock cycle per instruction ± Disadvantages ± Long cycle time ± Inefficient utilization of memory and function units
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op target address 0 26 31 6 bits 26 bits op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits MIPS Instruction Formats (Review) ± Three instruction formats ± R-type ± I-type ± J-type ± The different fields are: ± op: operation of the instruction ± rs, rt, rd: source/destination register specifiers ± shamt: shift amount ± funct: selects variant of the operation in the “op” field ± address/immediate: address offset or immediate value ± target address: target address of the jump instruction op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits op target address 0 26 31 6 bits 26 bits Subset differs somewhat from textbook for variety Subset differs somewhat from textbook for variety The MIPS Subset We Implement ± Add, subtract ± add rd, rs, rt ± sub rd, rs, rt ± OR Immediate ± ori rt, rs, imm16 ± Load, Store ± lw rt, rs, imm16 ± sw rt, rs, imm16 ± BRANCH ± beq rs, rt, imm16 ± JUMP: ± j target Implementation Overview ± Data “flows” through memory and functional units Registers Register # Data Register # Data memory Address Data Register # PC Instruction ALU Instruction memory Address Figure 5.1 from Text The Steps of Designing a Processor ± Instruction Set Architecture used to generate a high-level specification or Register-Transfer Level (RTL) simulation model ± Includes major organizational decisions ± Examples: no. and type of functional units, no. of register file ports ± Datapath-RTL refined to specify functional unit behavior and interfaces ± Datapath components ± Datapath interconnect ± Associated datapath “control points” ± Control structure defined and Control-RTL behavioral representation created ± RTL datapath and control design are refined to track physical design and functional validation ± Changes made for timing and errata (aka “bug”) fixes ±
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This note was uploaded on 08/22/2010 for the course CDA 3101 taught by Professor Staff during the Fall '07 term at University of Central Florida.

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1773238865 - Computer System Organization Computer...

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