fa99-eh-e2b

# fa99-eh-e2b - ECE 2030 Introduction to Computer Engineering...

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Unformatted text preview: ECE 2030 Introduction to Computer Engineering TEST 2 This examination is closed book, closed notes. No calculators are allowed. Show all of your work. State any assumptions you feel you need to make or ask for clarification. Make sure that your final answer for each question is clearly marked. I will provide scratch paper if needed. It must be turned in with your name on it. Question 1 2 3 4 5 6 Total Max Points 10 15 25 15 15 20 100 Graded Name: __________________________________________________________ Student Number: __________________________________________________ 2/5 1. (10 pts) Find the decimal equivalent of 0xF1 assuming the following: a. 2. 8-bit signed magnitude representation b. 8-bit two’ complement representation s (15 pts) Convert 0.87510 to its equivalent IEEE 754 floating point hexadecimal representation. Useful facts: • X, a floating point binary number, can be expressed by the formula X= –1S*1.F*2E-B • The format of the IEEE 754 standard for a 32-bit single-precision floating point operand is shown in the table below. S 1 bit Exponent 8 bits Fraction 23 bits S = ____________ (in binary) E = ___________________________________ (in binary) F = ___________________________________ (in binary) Hexadecimal representation (IEEE standard) ____________________________________ 3/5 3. (25 pts) A combinational circuit is defined by the following Boolean function: F(A,B,C) = Σm(0,2,3,7) a. Complete the truth table for F. ABC 000 001 011 010 100 101 111 110 b. F Implement the circuit with the 2-to-1 multiplexer shown below and external gates. Clearly label all input and output signals. Use input A to control the select line. 0 Out 1 c. S Implement the above circuit with the 3-to-8 decoder shown below and external gates. Clearly label all input and output signals. 0 2 21 22 0 1 2 3 4 5 6 7 4/5 4. (15 pts) Consider a single bit register cell constructed from a pair of transparent latches shown below. output input register cell phi1 phi2 Complete the timing diagram. Assume that the initial value of output is one. phi1 phi2 input output 5/5 5. (15 pts) A sequential network has one input (X) and one output (Z). The output is Z=1 iff the sequence 1111 is detected. Overlapping sequences are accepted. A sample is shown below: X= 0 0 1 1 1 1 1 0 1 1 1 1 0 Z= 0 0 0 0 0 1 1 0 0 0 0 1 0 Complete the state diagram below by adding all required transition arcs with appropriate input and output annotation. 00 6. 01 10 11 (20 pts) Circle the appropriate response, fill in the blank, or provide a short answer, as indicated. a. Adding 0x7B to 0x84 results in the following: ( overflow / carry / neither / both ), assuming 8-bit unsigned binary notation. b. There are two types of sequential circuits. Name one. __________________________________ c. In general, a demultiplexer has ___________ input line(s), _____________ output line(s), and ___________ select line(s). d. Enable inputs are often used in the implementation of circuits. Describe the behavior of a circuit with an Enable input when: i. ii. e. Enable is high Enable is low When we say a latch is transparent, what do we mean? ...
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## This note was uploaded on 08/23/2010 for the course EE 2030 taught by Professor Wills during the Spring '10 term at Georgia Tech.

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