Unformatted text preview: ECE 2030
INTRODUCTION TO COMPUTER ENGINEERING TEST 2 This examination is closed book, closed notes. No calculators are allowed. Show all
of your work. State any assumptions you feel you need to make or ask for
clarification. Make sure that your final answer for each question is clearly marked.
I will provide scratch paper if needed. It must be turned in with your name on it. Question
1
2
3
4
5
6
Total Max Points
10
15
25
15
15
20
100 Graded Name: __________________________________________________________
Student Number: __________________________________________________ 2/5 1. (10 pts) Find the decimal equivalent of 0x97 assuming the following:
a. 8bit signed magnitude representation b. 8bit two’ complement representation
s 23 2. 105 (15 pts) Convert 0.62510 to its equivalent IEEE 754 floating point hexadecimal representation.
Useful facts:
• X, a floating point binary number, can be expressed by the formula X= –1S*1.F*2EB
• The format of the IEEE 754 standard for a 32bit singleprecision floating point operand is shown
in the table below.
S
1 bit Exponent
8 bits Fraction
23 bits 0
S = ____________ (in binary)
01111110
E = ___________________________________ (in binary)
01000000000000000000000
F = ___________________________________ (in binary)
3F200000
Hexadecimal representation (IEEE standard) ____________________________________ 3/5 3. (25 pts) A combinational circuit is defined by the following Boolean function:
F(A,B,C) = Σm(2,5,6,7)
a. Complete the truth table for F. ABC
000
001
011
010
100
101
111
110
b. F
0
0
0
1
0
1
1
1 Implement the circuit with the 2to1 multiplexer shown below and external gates. Clearly label
all input and output signals. Use input A to control the select line. B
C 0 Out 1 B
C F S
A c. Implement the above circuit with the 3to8 decoder shown below and external gates. Clearly
label all input and output signals. C
B
A 0 2
21
22 0
1
2
3
4
5
6
7 F 4/5 4. (15 pts) Consider a single bit register cell constructed from a pair of transparent latches shown below. output input
register cell phi1 phi2 Complete the timing diagram. Assume that the initial value of output is zero. phi1 phi2 input output 5/5 5. (15 pts) A sequential network has one input (X) and one output (Z). The output is Z=1 iff the
sequence 0000 is detected. Overlapping sequences are accepted. A sample is shown below:
X= 1 1 0 0 0 0 0 1 0 0 0 0 1
Z= 0 0 0 0 0 1 1 0 0 0 0 1 0 Complete the state diagram below by adding all required transition arcs with appropriate input and
output annotation. 0/0 0/0 0/0 1/0
00 1/0
01 10 11 0/1 1/0
1/0 6. (20 pts) Circle the appropriate response, fill in the blank, or provide a short answer, as indicated.
a. Adding 0x7B to 0x75 results in the following: ( overflow / carry / neither / both ), assuming 8bit
signed binary notation. b. synchronous / asynchronous
There are two types of sequential circuits. Name one. ________________________________ c. 2n
1
In general, a demultiplexer has ___________ input line(s), _____________ output line(s), and
n
___________ select line(s). d. The priority encoder has an output called Valid. What is the output used for, i.e., what does it
mean when:
i. ii. e. Valid is high?
At least one data input is high; encoded value on output is valid Valid is low?
No data input line is high; value encoded on outputs of encoder is invalid When we say a latch is transparent, what do we mean?
the output sees the inputs immediately ...
View
Full
Document
This note was uploaded on 08/23/2010 for the course EE 2030 taught by Professor Wills during the Spring '10 term at Georgia Tech.
 Spring '10
 Wills

Click to edit the document details