sp10-lw-s3 - ECE 2030 1:00pm 4 problems 5 pages Problem 1(3...

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ECE 2030 1:00pm Computer Engineering Spring 2010 4 problems, 5 pages Exam Three 21 April 2010 Problem 1 (3 parts, 30 points) Memory Systems Part A (12 points) Consider a 1 Gbit DRAM chip organized as 128 million addresses of 8-bit words . Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal (not powers of two) . total number of bits in address 27 number of columns 2 30 = 2 15 = 32K column decoder required ( n to m ) 15 to 32K number of words per column 2 15 / 2 3 = 2 12 = 4K type of mux required ( n to m ) 4K to 1 number of address lines in column offset 12 Part B (10 points) Consider a memory system with 128 million addresses of 64-bit words using a 4 million address by 16-bit word memory DRAM chip. word address lines for memory system 27 chips needed in one bank 64/16 = 4 banks for memory system 2 27 / 2 22 = 2 5 = 32 memory decoder required ( n to m ) 5 to 32 decoder DRAM chips required 4*32 = 128 Part C (8 points) Design a 128 million address by 4 bit memory system with 32M x 4 memory chips. Label all busses and indicate bit width
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sp10-lw-s3 - ECE 2030 1:00pm 4 problems 5 pages Problem 1(3...

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