sp10-sw-s3 - ECE 2030 A 10:00am 4 problems, 4 pages...

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ECE 2030 A 10:00am Computer Engineering Spring 2010 4 problems, 4 pages Exam Three Solutions 21 April 2010 Problem 1 (3 parts, 30 points) Memory Systems Part A (10 points) Consider a 256 Mbit DRAM chip organized as 32 million addresses of one byte words . Assume both the DRAM cell and the DRAM chip is square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal . number of columns Sqrt(2 28 ) = 2 14 = 16K column decoder required ( n to m ) 14 to 16K type of mux required ( n to m ) 2K to 1 number of muxes required 8 number of address lines in column number log 2 (16K) = 14 number of address lines in column offset log 2 (2K) = 11 Part B (10 points) Consider a one Gbyte memory system with 128 million addresses of eight byte words using DRAM chips organized as 16 million addresses by 16 bit words. word address lines for memory system log 2 (128M) = 27 chips needed in one bank 8/2 = 64/16 = 4 banks for memory system 128M/16M = 8 memory decoder required ( n to m ) 3 to 8 DRAM chips required 4 x 8 = 32 Part C (10 points) (10 points) Design a 96M address x 4 bit memory system using 32M address x 4 bit memory chips. Label all busses and indicate bit width
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sp10-sw-s3 - ECE 2030 A 10:00am 4 problems, 4 pages...

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