sp09-sw-s3 - ECE 2030 A 10:00am 4 problems, 4 pages Problem...

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ECE 2030 A 10:00am Computer Engineering Spring 2009 4 problems, 4 pages Exam Three Solutions 8 April 2009 1 Problem 1 (2 parts, 24 points) Counters Part A (12 points) Design a toggle cell using transparent latches and basic gates. Use an icon for the latch. Your toggle cell should have an active high toggle enable input TE , and an active low clear input CLR ¯¯¯ , clock inputs Φ 1 and Φ 2 , and an output Out . The CLR ¯¯¯ signal has precedence over TE . Label all signals. Also complete the behavior table for the toggle cell. In Out En Latch In Out En Latch TE Out CLR Φ 1 Φ 2 TE CLR ¯¯¯ CLK Out 0 0 ↑↓ 0 1 0 ↑↓ 0 0 1 ↑↓ Q o 1 1 ↑↓ Q o ¯¯ Part B (12 points) Now combine these toggle cells to build a divide by six counter. Your counter should have an external clear, external count enable, and three count outputs O 2 , O 1 , O 0 . Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the toggle cells are already connected. Your design should support multi-digit systems . O 0 O 1 O 2 Ext Clr Ext CE TE Out Clr TE Out Clr TE Out Clr
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ECE 2030 A 10:00am Computer Engineering Spring 2009 4 problems, 4 pages Exam Three Solutions 8 April 2009 2 Problem 2 (2 parts, 18 points) Datapath Elements Part A (9 points) Consider the following input and output values for a shift operation. Determine
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sp09-sw-s3 - ECE 2030 A 10:00am 4 problems, 4 pages Problem...

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