fa08-sy-s1

# fa08-sy-s1 - ECE 2030 C&D Exam | Key 1 The Georgia Tech...

This preview shows pages 1–8. Sign up to view the full content.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ECE 2030 C&D Exam | Key 1. The Georgia Tech Honor Code governs this examination. 2. There are 9 questions and 11 pages including two blank worksheets. Make sure you have them all. 3. Please write/draw legibly. Use the work sheets for generating the solutions before providing the final answer. 4. State any assumptions you feel you have to make or ask for clarification. 5. Keep in mind it is difficult to give partial credit without written material. Please make sure you document any partial solutions. 6. The exam is 50 minutes. 7. Plan your work! Points are noted next to each problem. Problem Max Points Graded 1 10 2 10 3 10 4 10 5 10 6 5 7 10 8 10 9 15 Total 100 Student Name: Student Number: 1. Fill in the missing entries in the following table: Decimal 6-bit Binary 8-bit Binary Octal Hexadecimal 33 loom: 1H 2;“ #25 Qiiﬂii} 000mm} :31 1A 2. Provide a switch level implementation of the Boolean function defined by the following truth table: 55; i m z. HHHHOOOO> b—AHOOHHOOUJ r—tOHor—tor—AOO >—x o o o o >—* o GIFT] 3. Complete the following CMOS implementation by designing the pull down network. Provide expressions for OUT and OUT'. Vdd OUT: 85) OUT: QUE-4%) “PCE 4. Implement the following expression using only NOR and NOT gates. Use the mixed logic notation we have used in class. Do not assume that the complements of the inputs are available. Do not simplify the expression. Provide the number of transistors in the implementation. A and D are active low signals. F = (C(A' + B)')' + (D’E)' Number of Transistors: & 5. The following circuit was designed using a mixed logic design methodology. Write the Boolean expression that is computed by this circuit. A» B F 0— WM B‘ 5(713134-2» NBC—“3(3) C%— W"? HE :2 “(SCH st, :4} n (T @033 C_ D O 6. Consider the following gate level Circuit, propagation delays and its input waveform as shown. Draw the output waveform. You can assume that A, B, and C are low for all t such that t < 0. 7. Draw the DeMorgan equivalent gates. WW 8. The following is a truth table for a Boolean expression. a. Write the expression in sum—of—rninterrns form and product-of-maxterms forrn. A B c F 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 M1305): (F) [email protected]*C>(ﬂ+ (ﬂ + (3 44) .— WmW=éJELaﬁﬂﬂ?1ﬂ[email protected] b. Now simplify the SOP expression algebraically. . . :5») 47% if; 11' <5; :19; a" r _ “ ‘%/&é+iﬁ§}‘+g(aé *W“. . K w . ...
View Full Document

{[ snackBarMessage ]}

### Page1 / 8

fa08-sy-s1 - ECE 2030 C&D Exam | Key 1 The Georgia Tech...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online