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STUDENT NAME and NUMBER: (PLEASE PRINT CLEARLY) REMARKS: 1. All questions should be answered (in the space provided). 2. Books and notes may NOT be used, with the exception of one 8.5”x11” sheet of paper. DATE: November 30, 2000 TIME: 4:35 p.m. - 5:55 p.m. Marks: Total: Q1 Q2 Q3 Q4 v. 1.0 - 1 of 6 - Georgia Institute of Technology Department of Electrical and Computer Engineering Test #3 ECE2030: Introduction to Computer Engineering Q5 1. MEMORY SYSTEMS (MAX MARK: 25) a) You are given three different memory chips as listed in the table below. Fill in the remaining table cells with the total bits in each of the memory chips, the number of addressable locations, the number of address lines required to address all these locations, and the number of input/output data lines. Memory chip Total # of bits # of addresses # address lines # data lines 1Kx8 8,192 1,024 10 8 4Mx12 50,331,648 4,194,304 22 12 2Gx4 8,589,934,592 2,147,483,648 31 4 /20 /25 /20 /15 /20 /100
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ECE2030 Test #3 (continued) v. 1.0 - 2 of 6 - b) The module shown below is a 2Kx8 memory chip. Design a 4Kx16 bank of memory using multiple cop- ies of the 2Kx8 memory chip shown and whatever other combinational building blocks or logic elements you need. The inputs and outputs of your circuit should be the appropriate number of ADDRESS and DATA lines, as well as the MSEL (an enable to select the entire memory) and R/W lines to specify a read (or write) operation. It is OK to use “bus notation” to indicate multi-line datapaths, such as address and data lines.
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This note was uploaded on 08/23/2010 for the course EE 2030 taught by Professor Wills during the Spring '10 term at Georgia Institute of Technology.

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