fa03-sw-s1c

# fa03-sw-s1c - ECE 2030 C 11:00pm 4 problems 4 pages Problem...

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ECE 2030 C 11:00pm Computer Engineering Fall 2003 4 problems, 4 pages Exam One Solutions 17 September 2003 1 Problem 1 (3 parts, 30 points) Incomplete Circuits For each partial switch circuit below, complete the complementary switching network so the circuit contains no floats or short. Also write the Boolean expression computed by the completed circuit. Assume the inputs and their complements are available. F B C Out x E A Out z A B C D A D B Out y E C EF A C B D A B C E OUTx = F E D B C A + + + ) ( ) ( OUTy = C B A OUTz = E

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ECE 2030 C 11:00pm Computer Engineering Fall 2003 4 problems, 4 pages Exam One Solutions 17 September 2003 2 Problem 2 (2 parts, 24 points) Mixed Logic Reengineering A B C E F OUTx OUTy D G Part A (12 points) Write the output expression for the gate design shown above. Also determine the number of switches used in its implementation. OUTx = F E D C B A + + ) ( OUTy = G F E D + + ) # switches = 1 x 6 + 4 x 4 + 6 x 2 = 6 + 16 + 12 = 34T Part B (12 points) Reimplement the behavior below with a mixed logic design style using only AND gates and inverters. Determine the number of switches used in this implementation.
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## This note was uploaded on 08/23/2010 for the course EE 2030 taught by Professor Wills during the Spring '10 term at Georgia Tech.

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fa03-sw-s1c - ECE 2030 C 11:00pm 4 problems 4 pages Problem...

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