CS211Lecture3Module1

- CS 211 Computer Architecture Lecture 3 Instruction Level Parallelism and Its Dynamic Exploitation Instructor M Lancaster Instruction Level

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CS 211: Computer Architecture Lecture 3 Instruction Level Parallelism and Its Dynamic Exploitation Instructor: M. Lancaster
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02/06/2010 2 Instruction Level Parallelism Almost all processors since 1985 use pipelining to overlap the execution of instructions and improve performance. This potential overlap among instructions is called instruction level parallelism First introduced in the IBM Stretch (Model 7030) in about 1959 Later the CDC 6600 incorporated pipelining and the use of multiple functional units The Intel i486 was the first pipelined implementation of the IA32 architecture
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02/06/2010 3 Instruction Level Parallelism Instruction level parallel processing is the concurrent processing of multiple instructions Difficult to achieve within a basic code block Typical MIPS programs have a dynamic branch frequency of between 15% and 25% That is, between three and six instructions execute between a pair of branches, and data hazards usually exist within these instructions as they are likely to be dependent Given basic code block size in number of instructions, ILP must be exploited across multiple blocks
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02/06/2010 4 Instruction Level Parallelism The current trend is toward very deep pipelines, increasing from a depth of < 10 to > 20. With more stages, each stage can be smaller, more simple and provide less gate delay, therefore very high clock rates are possible.
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02/06/2010 5 Loop Level Parallelism Exploitation among Iterations of a Loop Loop adding two 1000 element arrays Code for (i=1; i<= 1000; i=i+1) x[i] = x[i] + y[i]; If we look at the generated code, within a loop there may be little opportunity for overlap of instructions, but each iteration of the loop can overlap with any other iteration
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02/06/2010 6 Concepts and Challenges Approaches to Exploiting ILP Two major approaches Dynamic – these approaches depend upon the hardware to locate the parallelism Static – fixed solutions generated by the compiler, and thus bound at compile time These approaches are not totally disjoint, some requiring both Limitations are imposed by data and control hazards
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02/06/2010 7 Features Limiting Exploitation of Parallelism Program features Instruction sequences Processor features Pipeline stages and their functions Interrelationships How do program properties limit performance? Under what circumstances?
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02/06/2010 8 Approaches to Exploiting ILP Dynamic Approach Hardware intensive approach Dominate desktop and server markets Pentium III, 4, Athlon MIPS R10000/12000 Sun UltraSPARC III PowerPC 603, G3, G4 Alpha 21264
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02/06/2010 9 Approaches to Exploiting ILP Static Approach Compiler intensive approach Embedded market and IA-64
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02/06/2010 10 Terminology and Ideas Cycles Per Instruction Pipeline CPI = Ideal Pipeline CPI + Structural Stalls + Data Hazard Stalls + Control Stalls Ideal Pipeline CPI is the max that we can achieve in a given
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This note was uploaded on 08/24/2010 for the course CS 211 taught by Professor Staff during the Spring '08 term at George Mason.

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- CS 211 Computer Architecture Lecture 3 Instruction Level Parallelism and Its Dynamic Exploitation Instructor M Lancaster Instruction Level

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