CS211Lecture3Module2

CS211Lecture3Module2 - CS 211: Computer Architecture...

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CS 211: Computer Architecture Lecture 3 Module 2 Basic Compiler Techniques for Exposing ILP Instructor: Morris Lancaster
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5/29/2008 CS 211 Lecture 3 Module 2 2 Basic Compiler Techniques for Exposing ILP Crucial for processors that use static issue, and important for processors that make dynamic issue decisions but use static scheduling
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5/29/2008 CS 211 Lecture 3 Module 2 3 Basic Pipeline Scheduling and Loop Unrolling Exploiting parallelism among instructions Finding sequences of unrelated instructions that can be overlapped in the pipeline Separation of a dependent instruction from a source instruction by a distance in clock cycles equal to the pipeline latency of the source instruction. (Avoid the stall) The compiler works with a knowledge of the amount of available ILP in the program and the latencies of the functional units within the pipeline This couples the compiler, sometimes to the specific chip version, or at least requires the setting of appropriate compiler flags
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5/29/2008 CS 211 Lecture 3 Module 2 4 Assumed Latencies Instruction Producing Result Instruction Using Result Latency In Clock Cycles (needed to avoid stall) FP ALU op Another FP ALU op 3 FP ALU op Store double 2 Load double FP ALU op 1 Load double Store double 0 Result of the load can be bypassed without stalling store
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This note was uploaded on 08/24/2010 for the course CS 211 taught by Professor Staff during the Spring '08 term at George Mason.

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CS211Lecture3Module2 - CS 211: Computer Architecture...

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