CS211Lecture4Module5

- CS 211 Computer Architecture Lecture 5 Overcoming Data Hazards with Dynamic Scheduling Instructor M Lancaster Dynamic Scheduling Using

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CS 211: Computer Architecture Lecture 5 Overcoming Data Hazards with Dynamic Scheduling Instructor: M. Lancaster
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05/30/2007 Lecture 3 Summer 2007 2 Dynamic Scheduling Using Tomasulo’s Approach Tomasulo invented the IBM 360/91 floating point unit Built before cache memories came into use The unit tracks when operands for instructions are available to minimize RAW hazards Used register renaming to minimize WAW and RAW hazards Key concept Track instruction dependences to allow execution as soon as operands were available and renaming registers to avoid WAR and WAW hazards Goal Achieve high floating point performance from the instruction set without relying on compiler
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05/30/2007 Lecture 3 Summer 2007 3 Tomasulo’s Approach - Background IBM 360/91 had only 4 double precision floating point registers IBM 360/91 had long memory accesses and long floating point delays IBM 360/91 has register-memory instructions Tomasulo’s algorithm focuses on the floating point unit and the load-store unit
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05/30/2007 Lecture 3 Summer 2007 4 Tomasulo’s Approach - Background RAW hazards – avoided by execution of an instruction only when its operands are available WAR and WAW hazards – eliminated by register renaming All destination registers renamed including those with pending read or write for an earlier instruction DIV.D F0 ,F2,F4 ADD.D F6 , F0 ,F8 S.D F6 ,0(R1) SUB.D F8,F10,F14 MUL.D F6 ,F10,F8 F8 must be used by ADD.D before SUB.D writes it or WAR hazard ADD.D must finish with R6 before S.D writes S.D must finish before write-back of MUL.D, WAW if ADD.D finishes later than MUL.D
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05/30/2007 Lecture 3 Summer 2007 5 Tomasulo’s Approach - Background S allows MUL.D to finish before ADD.D – removes F8 T allows SUB.D to finish before ADD.D Any subsequent uses of F8 must be replaced by T DIV.D F0 ,F2,F4 DIV.D F0,F2,F4 ADD.D F6 , F0 ,F8 ADD.D S ,F0,F8 S.D F6 ,0(R1) S.D S ,0(R1) SUB.D F8,F10,F14 SUB.D T ,F10,F14 MUL.D F6 ,F10,F8 MUL.D F6,F10, T
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05/30/2007 Lecture 3 Summer 2007 6 Tomasulo’s Approach - Background Register renaming is provided by reservation stations Buffer operands of instructions waiting to issue Fetches and buffers an operand as soon as it is available, eliminating need to get it from a register Pending instructions designate the reservation station that will provide their input. As instructions are issued, the register specifiers for pending operands are renamed to the names of the reservation station When successive writes to a register overlap in execution, only the last one is used to update the register There can be more reservation stations than real registers
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05/30/2007 Lecture 3 Summer 2007 7 Tomasulo’s Approach – Use of reservation stations rather than a centralized register file Hazard detection and execution control are distributed
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This note was uploaded on 08/24/2010 for the course CS 211 taught by Professor Staff during the Spring '08 term at George Mason.

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- CS 211 Computer Architecture Lecture 5 Overcoming Data Hazards with Dynamic Scheduling Instructor M Lancaster Dynamic Scheduling Using

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