CS211Lecture6module1

CS211Lecture6module1 - 1 CS 211 Computer Architecture...

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Unformatted text preview: 1/29/2010 1 CS 211: Computer Architecture Lecture 6 Exploiting Instruction Level Parallelism with Software Approaches Instructor: Morris Lancaster 1/29/2010 2 1/29/2010 CS 211 Lecture 6 2 Basic Compiler Techniques for Exposing ILP • Crucial for processors that use static issue, and important for processors that make dynamic issue decisions but use static scheduling 1/29/2010 3 5/30/3008 CS 211 Lecture 6 3 Basic Pipeline Scheduling and Loop Unrolling • Exploiting parallelism among instructions – Finding sequences of unrelated instructions that can be overlapped in the pipeline – Separation of a dependent instruction from a source instruction by a distance in clock cycles equal to the pipeline latency of the source instruction. (Avoid the stall) • The compiler works with a knowledge of the amount of available ILP in the program and the latencies of the functional units within the pipeline – This couples the compiler, sometimes to the specific chip version, or at least requires the setting of appropriate compiler flags 1/29/2010 4 CS 211 Lecture 6 4 Assumed Latencies Instruction Producing Result Instruction Using Result Latency In Clock Cycles (needed to avoid stall) FP ALU op Another FP ALU op 3 FP ALU op Store double 2 Load double FP ALU op 1 Load double Store double Result of the load can be bypassed without stalling store 1/29/2010 5 CS 211 Lecture 6 5 Basic Pipeline Scheduling and Loop Unrolling (cont) • Assume standard 5 stage integer pipeline – Branches have a delay of one clock cycle • Functional units are fully pipelined or replicated (as many times as the pipeline depth) – An operation of any type can be issued on every clock cycle and there are no structural hazards 1/29/2010 6 CS 211 Lecture 6 6 Basic Pipeline Scheduling and Loop Unrolling (cont) • Sample code For (i=1000; i>0; i=i-1) x[i] = x[i] + s; • MIPS code Loop: L.D F0,0(R1) ;F0 = array element ADD.D F4,F0,F2 ;add scalar in F2 S.D F4,0(R1) ;store back DADDUI R1,R1,#-8 ;decrement index BNE R1,R2,Loop ;R2 is precomputed so that ;8(R2) is last value to be ;computed 1/29/2010 7 CS 211 Lecture 6 7 Basic Pipeline Scheduling and Loop Unrolling (cont) • MIPS code Loop: L.D F0,0(R1) ;1 clock cycle stall ;2 ADD.D F4,F0,F2 ;3 stall ;4 stall ;5 S.D F4,0(R1) ;6 DADDUI R1,R1,#-8 ;7 stall ;8 BNE R1,R2,Loop ;9 1/29/2010 8 CS 211 Lecture 6 8 Rescheduling Gives • Sample code For (i=1000; i>0; i=i-1) x[i] = x[i] + s; • MIPS code Loop: L.D F0,0(R1) 1 DADDUI R1,R1,#-8 2 ADD.D F4,F0,F2 3 stall 4 BNE R1,R2,Loop 5 S.D F4,8(R1) 6 1/29/2010 9 CS 211 Lecture 6 9 Unrolling Gives • MIPS code Loop: L.D F0,0(R1) ADD.D F4,F0,F2 S.D F4,0(R1) L.D F6,-8(R1) ADD.D F8,F6,F2 S.D F8,-8(R1) L.D F10,-16(R1) ADD.D F12,F10,F2 S.D F12,-16(R1) L.D F14,-24(R1) ADD.D F16,F14,F2 S.D F16,-24(R1) DADDUI R1,R1,#-32 BNE R1,R2,Loop 1/29/2010 10 CS 211 Lecture 6 10 Unrolling and Removing Hazards Gives • MIPS code Loop: L.D F0,0(R1) ;total of 14 clock cycles L.D F6,-8(R1) L.D F10,-16(R1) L.D F14,-24(R1)...
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CS211Lecture6module1 - 1 CS 211 Computer Architecture...

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