Chapter2-dynamic-sched

Chapter2-dynamic-sched - Csci 211 Computer System...

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Csci 211 Computer System Architecture Lec 4 – Instruction Level Parallelism Adapted from the slides by Dr. David Patterson @ UC Berkeley Xiuzhen Cheng Department of Computer Sciences The George Washington University
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08/24/10 Csci 211 – Lecture 4 2 Outline ILP Compiler techniques to increase ILP Loop Unrolling Static Branch Prediction Dynamic Branch Prediction Overcoming Data Hazards with Dynamic Scheduling (Start) Tomasulo Algorithm Conclusion
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08/24/10 Csci 211 – Lecture 4 3 Recall from Pipelining Review Pipeline CPI = Ideal pipeline CPI + Structural Stalls + Data Hazard Stalls + Control Stalls Ideal pipeline CPI : measure of the maximum performance attainable by the implementation Structural hazards : HW cannot support this combination of instructions Data hazards : Instruction depends on result of prior instruction still in the pipeline Control hazards : Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps)
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08/24/10 Csci 211 – Lecture 4 4 Instruction Level Parallelism Instruction-Level Parallelism ( ILP ): overlap the execution of instructions to improve performance Two approaches to exploit ILP: 1) Rely on hardware to help discover and exploit the parallelism dynamically (e.g., Pentium 4, AMD Opteron, IBM Power) , and 2) Rely on software technology to find parallelism, statically at compile-time (e.g., Itanium 2) – Appendix G Next 3 lectures on this topic
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08/24/10 Csci 211 – Lecture 4 5 Instruction-Level Parallelism (ILP) Basic Block (BB) ILP is quite small BB: a straight-line code sequence with no branches in except to the entry and no branches out except at the exit average dynamic branch frequency 15% to 25% => 4 to 7 instructions execute between a pair of branches Plus instructions in BB likely to depend on each other To obtain substantial performance enhancements, we must exploit ILP across multiple basic blocks Simplest: loop-level parallelism to exploit parallelism among iterations of a loop. E.g., for (i=1; i<=1000; i=i+1) x[i] = x[i] + y[i];
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08/24/10 Csci 211 – Lecture 4 6 Loop-Level Parallelism Exploit loop-level parallelism by “unrolling loop” either by 1. dynamic via branch prediction or 2. static via loop unrolling by compiler (Another way is vectors, will be covered if time permits) Determining instruction dependence is critical to Loop Level Parallelism If 2 instructions are parallel , they can execute simultaneously in a pipeline of arbitrary depth without causing any stalls (assuming no structural hazards) dependent , they are not parallel and must be executed in order, although they may often be partially overlapped
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08/24/10 Csci 211 – Lecture 4 7 Instr J is data dependent (aka true dependence ) on Instr I: 1. Instr J tries to read a result produced by Instr I 2. or Instr J is data dependent on Instr K which is dependent on Instr I If two instructions are data dependent, they cannot execute simultaneously or be completely overlapped
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Chapter2-dynamic-sched - Csci 211 Computer System...

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