Chapter1 - CSCI 211 Computer System Architecture Lec 1...

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CSCI 211 Computer System Architecture Lec 1 - Introduction Xiuzhen Cheng Department of Computer Sciences The George Washington University Adapted from the slides by Dr. David Patterson @ UC Berkeley
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08/24/10 Csci 211 – Lecture 1 2 Outline Computer Science at a Crossroads Computer Architecture v. Instruction Set Arch. What Computer Architecture brings to table Technology Trends: Culture of tracking, anticipating and exploiting advances in technology Careful, quantitative comparisons: 1. Define and quantify dependability 2. Define and quantify power 3. Define, quantify, and summarize relative performance 4. Define and quantify relative cost
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08/24/10 Csci 211 – Lecture 1 3 Old Conventional Wisdom: Power is free, Transistors expensive New Conventional Wisdom: “Power wall” Power expensive, Xtors free (Can put more on a chip than can afford to turn them on) Old CW: Sufficiently increasing Instruction Level Parallelism via compilers, innovation (Out-of-order, speculation, VLIW, …) New CW: “ILP wall” - law of diminishing returns on more HW for ILP Old CW: Multiplies are slow, Memory access is fast New CW: “Memory wall” - Memory slow, multiplies fast (200 clock cycles to DRAM memory, 4 clocks for multiply) Old CW: Uniprocessor performance 2X / 1.5 yrs New CW: Power Wall + ILP Wall + Memory Wall = Brick Wall Uniprocessor performance now 2X / 5(?) yrs Sea change in chip design: multiple “cores” (2X processors per chip / ~ 2 years) » More simpler processors are more power efficient Crossroads: Conventional Wisdom in Comp. Arch
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08/24/10 Csci 211 – Lecture 1 4 1 10 100 1000 10000 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 Performance (vs. VAX-11/780 25%/year 52%/year ??%/year Crossroads: Uniprocessor Performance VAX : 25%/year 1978 to 1986 RISC + x86: 52%/year 1986 to 2002 RISC + x86: 20%/year 2002 to present From Hennessy and Patterson, Computer Architecture: A Quantitative Approach , 4th edition, October, 2006
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08/24/10 Csci 211 – Lecture 1 5 Sea Change in Chip Design Intel 4004 (1971): 4-bit processor, 2312 transistors, 0.4 MHz, 10 micron PMOS, 11 mm 2 chip Processor is the new transistor? RISC II (1983): 32-bit, 5 stage pipeline, 40,760 transistors, 3 MHz, 3 micron NMOS, 60 mm 2 chip 125 mm 2 chip, 0.065 micron CMOS = 2312 RISC II+FPU+Icache+Dcache – RISC II shrinks to ~ 0.02 mm 2 at 65 nm Caches via DRAM or 1 transistor SRAM ( www.t-ram.com ) ? – Proximity Communication via capacitive coupling at > 1 TB/s ? (Ivan Sutherland @ Sun / Berkeley)
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08/24/10 Csci 211 – Lecture 1 6 Déjà vu all over again? Multiprocessors imminent in 1970s, ‘80s, ‘90s, … “… today’s processors … are nearing an impasse as technologies approach the speed of light. .” David Mitchell, The Transputer: The Time Is Now ( 1989 ) Transputer was premature Custom multiprocessors strove to lead uniprocessors Procrastination rewarded: 2X seq. perf. / 1.5 years “We are dedicating all of our future product development to multicore designs. … This is a sea change in computing” Paul Otellini, President, Intel ( 2004 ) Difference is all microprocessor companies switch to
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Chapter1 - CSCI 211 Computer System Architecture Lec 1...

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