Chapter4-directory

Chapter4-directory - CSCI 211 Computer System Architecture...

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Xiuzhen Cheng Department of Computer Sciences The George Washington University Adapted from the slides by Dr. David Patterson @ UC Berkeley CSCI 211 Computer System Architecture Lec 9 – Multiprocessor II
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08/24/10 Csci 211 – Lec 9 2 Review Caches contain all information on state of cached memory blocks Snooping cache over shared medium for smaller MP by invalidating other cached copies on write Sharing cached data Coherence (values returned by a read), Consistency (when a written value will be returned by a read)
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08/24/10 Csci 211 – Lec 9 3 Outline Review Coherence traffic and Performance on MP Directory-based protocols and examples Synchronization Relaxed Consistency Models Fallacies and Pitfalls Conclusion
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08/24/10 Csci 211 – Lec 9 4 Performance of Symmetric Shared-Memory Multiprocessors Cache performance is combination of 1. Uniprocessor cache miss traffic 2. Traffic caused by communication Results in invalidations and subsequent cache misses 4 th C: coherence miss Joins Compulsory, Capacity, Conflict
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08/24/10 Csci 211 – Lec 9 5 Coherency Misses 1. True sharing misses arise from the communication of data through the cache coherence mechanism Invalidates due to 1 st write to shared block Reads by another CPU of modified block in different cache Miss would still occur if block size were 1 word 2. False sharing misses when a block is invalidated because some word in the block, other than the one being read, is written into Invalidation does not cause a new value to be communicated, but only causes an extra cache miss Block is shared, but no word in block is actually shared miss would not occur if block size were 1 word
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08/24/10 Csci 211 – Lec 9 6 Example: True v. False Sharing v. Hit? Time P1 P2 True, False, Hit? Why? 1 Write x1 2 Read x2 3 Write x1 4 Write x2 5 Read x2 Assume x1 and x2 in same cache block. P1 and P2 both read x1 and x2 before. True miss; invalidate x1 in P2 False miss; x1 irrelevant to P2 False miss; x1 irrelevant to P2 False miss; x1 irrelevant to P2 True miss; invalidate x2 in P1
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08/24/10 Csci 211 – Lec 9 7 MP Performance 4 Processor Commercial Workload: OLTP, Decision Support (Database), Search Engine 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 1 MB 2 MB 4 MB 8 MB Cache size Instruction Capacity/Conflict Cold False Sharing True Sharing True sharing and false sharing unchanged going from 1 MB to 8 MB (L3 cache) Uniprocessor cache misses improve with cache size increase (Instruction, Capacity/Conflict, Compulsory) (Memory) Cycles per Instruction
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08/24/10 Csci 211 – Lec 9 8 MP Performance 2MB Cache Commercial Workload: OLTP, Decision Support (Database), Search Engine True sharing, false sharing increase going from 1 to 8 CPUs 0 0.5 1 1.5 2 2.5 3 1 2 4 6 8 Processor count Instruction Conflict/Capacity Cold False Sharing True Sharing (Memory) Cycles per Instruction
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08/24/10 Csci 211 – Lec 9 9 A Cache Coherent System Must: Provide set of states, state transition diagram, and actions Manage coherence protocol (0)
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Chapter4-directory - CSCI 211 Computer System Architecture...

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