Homework4

# Homework4 - Homework 4 Due 6/02/09 Problem 1. Calculation...

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Homework 4 Due 6/02/09 ECE 165, Prof. Buckwalter 1 Problem 1 . Calculation of Latch and Register Timing (60) A) Calculate the intrinsic delay for the inverter driving a transmission gate assuming both devices are minimum sized using the equivalent circuit above. Provide tplh and tphl values referenced to tpo. (15) The transmission gate can now be used to create a D-FF. Two latches are cascaded to make a D flip-flop. Two inverters provide the clk and clk bar signals. Consider these delays in the next cal- culations. B) Show the circuit path (inside of the latches) that determine the set-up and hold times. (5) C) Calculate in terms of tpo the set-up time. What is the set-up time if tpo=16ps (10)? D) Calculate the hold time in terms of tpo. What is the hold time if tpo=16ps (10)? E) Calculate the clk-to-q delay in terms of tpo and provide a value for tpo = 16ps. (10) F) Calculate the maximum divide frequency for the DFF. Does it match your simulations? (10)

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Homework 4 Due 6/02/09 ECE 165, Prof. Buckwalter 2 Problem 2 . Pipelined Circuits. (15) In the following figure, a combinational network consisting
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## This note was uploaded on 08/26/2010 for the course ECE ECE 165 taught by Professor Buckwalter during the Spring '09 term at UCSD.

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Homework4 - Homework 4 Due 6/02/09 Problem 1. Calculation...

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