Homework4_solution

Homework4_solution - Problem 1. A. where it is R eqp R eqp...

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Problem 1. A.  10 0.69 R 5 R R R 2 0.69 5R R 3 RR 10 0.69 5 R R 2 0.69 5 R 22 3 pHL eqn eqn eqn eqp eqn eqn eqp eqp pLH eqn eqp eqn eqn tC C C C C R C C     where it is assumed 2 eqp eqn R R and the parallel combination is roughly equal to Reqn. 25 25 0.69 3 39 p eqn po po tR C t t  . Since 3 0.69 0.69 3 eqp po eqn eqn R R C R B. C) When we consider a clock path, we need to additionally consider the clock inverter delay. The clock path delay accounts for
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, ,, 17 14 33 11 4 pc lkb po lk tt t t t      where the factor of 1/3 arises from the TG logical effort. Note that the clkb drives the clk. The set-up time is given by the intrinsic delay of the first inverter/TG combination, the load of the output inverter (assuming it drives a minimum size inverter on the output), and finally the load of the final inverter/TG combination. (3 1 1 2 1) 8 128 su po po t p s Since the clock is delayed with respect to the relative timing at the transmission gate and at the data input. The set-up time might be relaxed by the propagation time through the clock path.
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This note was uploaded on 08/26/2010 for the course ECE ECE 165 taught by Professor Buckwalter during the Spring '09 term at UCSD.

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Homework4_solution - Problem 1. A. where it is R eqp R eqp...

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