Chapter12

Chapter12 - Integrated Integrated Circuits Circuits A...

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© Digital Integrated Circuits 2nd Memories Integrated Integrated Circuits Circuits A Design A Design Perspective Perspective Semiconductor Semiconductor Memories Memories Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic December 20, 2002
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© Digital Integrated Circuits 2nd Memories Chapter Overview Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
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© Digital Integrated Circuits 2nd Memories Semiconductor Memory Classification Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO
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© Digital Integrated Circuits 2nd Memories Memory Timing: Definitions Definitions Write cycle Read access Read access Read cycle Write access Data written Data valid DATA WRITE READ
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© Digital Integrated Circuits 2nd Memories Memory Architecture: Decoders Decoders Word 0 Word 1 Word 2 Word N 2 2 N 2 1 Storage cell M bits M S 0 S 1 S 2 S N 2 2 A 0 A 1 A K 2 1 K 5 log 2 N S N 2 1 N 2 2 N 2 1 Storage cell S 0 Input-Output ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals ( M
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© Digital Integrated Circuits 2nd Memories Row Decoder Bit line 2 L 2 K Word line A K A K 1 1 A L 2 1 A 0 M. 2 K A K 2 1 Sense amplifiers / Drivers Column decoder Input-Output ( M bits) Array-Structured Memory Architecture Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH Amplify swing to rail-to-rail amplitude Selects appropriate word
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© Digital Integrated Circuits 2nd Memories Hierarchical Memory Architecture Architecture Advantages: 1. Shorter wires within blocks 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings 2. Block address activates only 1 block => power savings Global amplifier/driver Control circuitry Global data bus Block selector Block 0 Row address Column address Block address i P 2 1 I/O
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© Digital Integrated Circuits 2nd Memories Block Diagram of 4 Mbit SRAM SRAM Clock generator CS, WE buffer I/O buffer Y -address buffer X -address buffer x1/x4 controller Z -address buffer X -address buffer Predecoder and block selector Bit line load Transfer gate Column decoder Sense amplifier and write driver [Hirose90]
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© Digital Integrated Circuits 2nd Memories Contents-Addressable Memory Memory Address Decoder Data (64 bits) I/O Buffers Comparand CAM Array 2 9 words3 64 bits Mask Control Logic R/W Address (9 bits) Commands 2 9 Validity Bits Priority Encoder
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© Digital Integrated Circuits 2nd Memories Memory Timing: Approaches Approaches DRAM Timing Multiplexed Adressing SRAM Timing Self-timed Address bus RAS - CAS timing Row Address Address Bus Address transition initiates memory operation Address Column Address CAS
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© Digital Integrated Circuits 2nd Memories Read-Only Memory Cells Read-Only Memory Cells WL BL WL BL 1 WL BL WL BL WL BL 0 V DD WL BL GND Diode ROM MOS ROM 1 MOS ROM 2
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This note was uploaded on 08/26/2010 for the course ECE ECE 165 taught by Professor Buckwalter during the Spring '09 term at UCSD.

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Chapter12 - Integrated Integrated Circuits Circuits A...

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