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Unformatted text preview: Problem 1 a) xd = Ld − L 200nm − 100nm = = 50nm 2 2 Cgs = Cgd = Cox xdW = 10 fF ( 0.05μ m )(1μ m ) = 0.5 fF μ m2 fF Cg = Cox LdW = 10 ( 0.2μ m )(1μ m ) = 2 fF μ m2 b) ReqN = ReqP 3 Vdd 3 1V = = 7.5k Ω ⋅ μ m 4 I dsat , N 4 0.1 mA μm 3 Vdd 3 1V = = = 30k Ω ⋅ μ m 4 I dsat , N 4 0.025 mA μm Problem 2 I dsat , N = I dsat , P W Wn ' Vdsat , N (VM − VTN − Vdsat , N 2 ) = k p p Vdsat , P (VM − Vdd − VTP − Vdsat , P 2 ) L L ' ' knWn = k pW p → W p WN = 4
' kn Problem 3 a) t pHL = 0.69 Reqn CL t pLH = 0.69 Reqp CL CL = 2 ( Cgdn + C gdp ) = 2Cox xd (W p + Wn ) = 1 fF (W p + Wn ) ⎛ Wp ⎞ ⎛ Wp ⎞ t pHL = 0.69 ⋅ 7.5k Ω ⋅1 fF ⎜1 + ⎟ = 5.2 ps ⎜1 + ⎟ ⎝ Wn ⎠ ⎝ Wn ⎠ ⎛W t pLH = 0.69 ⋅ 30k Ω ⋅1 fF ⎜1 + n ⎜ Wp ⎝ ⎞ ⎛W ⎟ = 20.8 ps ⎜1 + n ⎟ ⎜ Wp ⎠ ⎝ ⎞ ⎟ ⎟ ⎠ b) tp = ⎛⎛ W 1 ( t pLH + t pHL ) = 5.2 ps ⎜ ⎜1 + Wp ⎜⎝ 2 n ⎝
dt p dW p =0→ Wp Wn ⎞ ⎛ Wn ⎟ + 4 ⎜1 + ⎜ ⎠ ⎝ Wp ⎞⎞ ⎟⎟ ⎟⎟ ⎠⎠ = 2 c) ⎛ ⎛ 1 ⎞⎞ t p = 5.2 ps ⎜ (1 + 2 ) + 4 ⎜1 + ⎟ ⎟ = 46.8 ps ⎝ 2 ⎠⎠ ⎝ CL = ( Cgdn + C gdp ) + 4Cg = Cox (W p + Wn ) ( xd + 4 L ) CL = 10 fF ( 3μ m )( 0.05μ m + 0.4μ m ) = 13.5 fF μ m2 2 Pdyn = CLVdd f = 13.5μW d) 2 PDP = Pdyn ⋅ t p = CLVdd 2 We can conclude that energy consumption (PDP) can be minimized by reducing CL by moving to smaller channel lengths or minimizing gate sizing to lower total capacitance or by minimizing the power supply. Problem 4. a) b) c) d) Problem 5. a) N = log 4 F = log 4 1024 = 5 S i = 4i d min = N (1 + f ) = 5 ⋅ (1 + 4 ) = 25 d = 1 + F = 1025 t pHL = 0.69 ReqN 4C + 2 ReqN 6C + ( 2 ReqN + ReqP ) 8C = 0.69 ( 32 ReqN + 8 ReqP ) C t pLH
eqP 8C + 2 ReqP 6C + ( 2 ReqP + ReqN eqN ( = 0.69 ( R ) ) 4C ) = 0.69 ( 4R + 28ReqP ) C b) tp = 0.69 ( 4 ReqN + 28ReqP + 32 ReqN + 8ReqP ) C = 0.69 ⋅18 ⋅ ( ReqN + ReqP ) C 2 Since for an inverter, t po = 0.69 ( ReqN + ReqP ) 3C The tristate buffer experiences a delay of t p = 6t po . Problem 6. a) Logical effort g= Cinput , gate Cinput ,inv Wp ⎞ ⎛ ⎜N + ( NWn + Wp ) = ⎝ Wn ⎟ = ( N + 3) = ( N + 3) ⎠ g NAND = 4 (Wn + Wp ) ⎛1 + Wp ⎞ (1 + 3) ⎜ ⎟ ⎝ Wn ⎠ Wp ⎞ ⎛ ⎜1 + N (Wn + NWp ) = ⎝ Wn ⎟ = (1 + 3N ) = (1 + 3N ) ⎠ g NOR = Wp ⎞ 4 (Wn + Wp ) ⎛1 + ⎟ (1 + 3) ⎜ ⎝ Wn ⎠
b) Intrinsic delay p= Cint rinsic , gate Cint rin si c ,inv pNAND ( NW = (W n n + NW p ) + Wp ) =N pNOR ( NW = (W n n + NW p ) + Wp ) =N ...
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This note was uploaded on 08/26/2010 for the course ECE ECE 165 taught by Professor Buckwalter during the Spring '09 term at UCSD.
 Spring '09
 BUCKWALTER

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