LAB-08 - ESE 382 Digital System Design Using VHDL and PLDs...

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1 ESE 382 Digital System Design Using VHDL and PLDs PRELIMINARY PRELIMINARY PRELIMINARY PRELIMINARY Spring 10, Ken Short March 22, 2010 1:43 pm Laboratory 8: Sequential System Hardware Testbench for Multifunction Expandable 8- Input Gate This laboratory is to be performed the week starting April 4th. Prerequisite Reading 1. Chapters 8 and 9 of the text. 2. CD4048 Multifunction 8-Input Gate data sheet. Purpose The purpose of this laboratory is to provide you with your first experience in designing and imple- menting a sequential system using VHDL and PLDs. You will write a description for a sequential system that provides a hardware test station (hardware testbench) for the combinational design of Laboratory 5, the Multifunction Expandable 8-Input Gate. The hardware test station for Laboratory 5 was designed by Frank Wu. Frank used an ATmega16 microcontroller to provide a sequence of stimulus values simultaneously to an actual CD4048 Multifunction 8-Input Gate IC and to the PLD that was being tested. Thus, the CD4048 served as the “Golden Model.” After applying each stimulus value, the ATmega16 waited for a length of time greater than the propagation delay of the PLD, then read the output from the CD4048 and from the PLD. If the outputs were the same, the microcontroller generated the next stimulus value. If the outputs differed, the microcontroller held the stimulus value constant and lighted an LED indicating a failure. Other LEDs, displayed the stimulus value generated by the ATmega16,
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LAB-08 - ESE 382 Digital System Design Using VHDL and PLDs...

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