Lab09s10_1 - ESE 382 Digital System Design Using VHDL and...

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1 ESE 382 Digital System Design Using VHDL and PLDs PRELIMINARY PRELIMINARY PRELIMINARY PRELIMINARY Spring 10, Ken Short April 5, 2010 9:23 am Laboratory 9: SPI Transmitter This laboratory is to be performed the week starting April 11th. Prerequisite Reading 1. Chapter 10 of the text. 2. M68HC11E Family Data Sheet, Chapter 8 SPI. 3. Atmel ATmega128 Data Sheet, pages 165 through 173, Chapter 19 Serial Peripheral Interface. Purpose The Serial Peripheral Interface (SPI) is a synchronous serial bus interface commonly used to transfer information between integrated circuits. A system implemented as a FPGA often has a SPI interface so that it can communicate with other ICs in a larger system. The project that you will implement over the next few laboratories involves the design of a SPI system, implemented using VHDL and a FPGA, that can be used to test other systems having SPI interfaces. SPI is a de facto standard that was originally developed by Motorola. As a de facto standard, there is no official standard document. A practical reference to define SPI is a chapter in a Motorola microcontroller user’s manual, such as reference 2 above. Another reference that we will use is the Atmel ATmega128 microcontroller data sheet, reference 3 above. We will most closely follow the signal and bit names used in the Atmel data sheet. This laboratory focuses on implementing part of the transmission functionality of an SPI master. The next few laboratories add components until we have a complete system. A block diagram of the system for this laboratory is: This system consists of two components and a top-level structural architecture.
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2 Design Tasks Task1: Send Positive Edge Detector A debounced pushbutton is to be used to provide a positive pulse send signal to indicate when the system is to serially transmit a byte of data. The debounced pushbutton generates this pulse for as long as it is pressed. Thus, the pulse may be very long in comparison to the time it takes to transmit the entire byte of data. If the system were to use the level of the send signal to deter- mine when to transmit the data byte, it could end up sending the same byte multiple times for one press of the pushbutton. To eliminate this possibility, a positive edge detector is used to detect the
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Lab09s10_1 - ESE 382 Digital System Design Using VHDL and...

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