Lab11s10 - ESE 382 Digital System Design Using VHDL and...

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1 ESE 382 Digital System Design Using VHDL and PLDs PRELIMINARY PRELIMINARY PRELIMINARY PRELIMINARY Spring 10, Ken Short revised April 19, 2010 7:15 am Laboratory 11: SPI Test System III This laboratory is to be performed the week starting April 25th. Prerequisite Reading 1. Chapter 10 of the text. 2. M68HC11E Family Data Sheet, Chapter 8 SPI. 3. MAX5402 256 Tap Digital Potentiometer. 4. MAX1106 8-bit Serial Analog-to-Digital Converter. Purpose In this laboratory the functionality of the SPI master, designed in Laboratories 9 and 10, is further extended. In the previous design the frequency of the SPI shift clock sck was and integer fraction of the external system clock clk . The smallest integer divisor would be 2 making sck half the frequency of clk . To match the sck frequency to the needs of a single slave with a known fixed relationship between sck and clk , we can change the frequency of clk . But, constantly chang- ing the external system clock to accommodate different slaves is inconvenient. Instead, we want to use a fixed system clock frequency and have inputs to our system that let us select a frequencies that are a fraction of the system clock frequency. A block diagram of the system for this laboratory is: This system consists of four components and a top-level structural architecture.
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Lab11s10 - ESE 382 Digital System Design Using VHDL and...

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