Lab10s10 - ESE 382 Digital System Design Using VHDL and...

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ESE 382 Digital System Design Using VHDL and PLDs PRELIMINARY PRELIMINARY PRELIMINARY PRELIMINARY Spring 10, Ken Short April 11, 2010 11:15 am Laboratory 10: SPI Transmitter and Receiver This laboratory is to be performed the week starting April 18th. Prerequisite Reading 1. Chapter 10 of the text. 2. M68HC11E Family Data Sheet, Chapter 8 SPI. 3. Atmel ATmega128 Data Sheet, pages 165 through 173, Chapter 19 Serial Peripheral Interface. Purpose In this laboratory the functionality of the SPI master, designed in Laboratory 9, is extended. A DORD input is added. This input selects whether the serial byte is transmitted most significant bit first or least significant bit first. A MISO input is also added. This input receives serial data sent from the slave to the master. The byte received is output at data_out . A block diagram of the system for this laboratory is: This system consists of three components and a top-level structural architecture. Design Tasks Task1: Data Order Selection When the data order input dord is 0 at the start of a transmission, the data_in byte is transmit- ted most significant bit first. When the data order input is 1 at the start of a transmission, the data_in byte is transmitted least significant bit first. This feature is implemented by modifica- tion of entity spi_tx_shifter . The entity declaration for
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  • Spring '10
  • short
  • Serial Peripheral Interface Bus, std_logic, data order, serial data, non self-checking testbench, data order input

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Lab10s10 - ESE 382 Digital System Design Using VHDL and...

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