Lab07s10 - ESE 382 Digital System Design Using VHDL and...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ESE 382 Digital System Design Using VHDL and PLDs Spring 10, Ken Short Laboratory 7: Selfchecking Testbenches for Combinational Systems This laboratory is to be performed the week starting March 21st. Prerequisite Reading 1. Chapter 7 of the text. 2. 74F537 1-of-3 Decoder with Three-state Outputs Data Sheet. Purpose In this laboratory you will write design descriptions and selfchecking testbenches for three combi- national systems. Selfchecking testbenches have the advantage that simulation waveforms do not have to be exam- ined in detail to verify the UTT. The testbench compares the actual UUT outputs to the expected outputs for each input combination applied to the UUT. A message is displayed indicating for which input combinations the actual output differs from the expected output. Selfchecking test- benches differ in how they determine the expected outputs. There are two basic approaches, either include the expected output values as constants in the testbench or have the testbench compute the expected output for each input combination, When writing a testbench for a combinational system a decision must be made whether or not to have the testbench provide an exhaustive verification. An exhaustive verification applies every possible input combination and checks each output. The time required for the simulation increases exponentially with the number of system inputs. If something less than an exhaustive verification is performed, careful thought must be given as to what input combinations need to be applied to
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 08/30/2010 for the course ESE 382 taught by Professor Short during the Spring '10 term at SUNY Stony Brook.

Page1 / 3

Lab07s10 - ESE 382 Digital System Design Using VHDL and...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online