Lab03s10_r1 - ESE 382 Digital System Design Using VHDL and...

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1 ESE 382 Digital System Design Using VHDL and PLDs Spring 10, Ken Short February 16, 2010 8:16 pm Laboratory 3: Dataflow Style Combinational Design This laboratory is to be performed the week starting Feb. 21st. Prerequisite Reading 1. Chapter 4 of the text. 2. Help file documentation on workspaces in the folder Course Documents > Aldec Documents on Blackboard. This information is from the Active HDL Help Menu. Purpose The purpose of this laboratory is to reinforce your understanding of the VHDL design flow intro- duced in Laboratories 1 and 2, and to introduce dataflow architectures for combinational design. You will create your own VHDL design descriptions (using dataflow architectures) for a full- adder combinational circuit. You will perform functional simulations of your design descriptions and a timing simulation of the timing model produced by the place and route tool. Finally, you will program a ispGAL22V10C-10LJ SPLD and verify its operation using a custom built test sta- tion. Any combinational function can be described using a canonical sum-of-products (CSOP) Boolean expression. Such an expression consists of the logical sum of the function’s minterms. This is a straight forward, though not concise, way of expressing a combinational function. Since the syn- thesizer and place-and-route tool minimize the CSOP Boolean expression, the implemented logic corresponds to the simplified sum-of-products for the function. Alternatively, any combinational function can be written in a canonical product-of-sums (CPOS) Boolean expression. Such an expression consists of the logical product of the function’s max- terms. This is also a straight forward, though not concise, way of expressing a combinational function. The synthesizer and place-and-route tool also minimize the CPOS Boolean expression and the implemented logic corresponds to the simplified product-of-sums expression for the func- tion. There are actually two forms of concurrent signal assignment statements: selected and condi- tional. A Boolean expression concurrent signal assignment statement is a simplified form of a conditional signal assignment statement. However, for instructional purposes we treat the Bool- ean expression form separately. As a result, three kinds of concurrent signal assignment state- ments are considered: • Concurrent signal assignment statement using a Boolean expression • Selected signal assignment statement • Conditional signal assignment statement
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This note was uploaded on 08/30/2010 for the course ESE 382 taught by Professor Short during the Spring '10 term at SUNY Stony Brook.

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Lab03s10_r1 - ESE 382 Digital System Design Using VHDL and...

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