lab02bs10 - ESE 382 Digital System Design Using VHDL and...

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1 ESE 382 Digital System Design Using VHDL and PLDs Spring 10, Ken Short Laboratory 2b: VHDL/PLD Design Flow - Timing Simulation, and Programming a SPLD This laboratory is to be performed the week starting Feb. 7th along with Laboratory 2. Prerequisite Reading 1. Sections 1.10 through 1.15 of text Purpose The purpose of this laboratory is to complete the VHDL design flow example from Laboratories 1 and 2 by performing a timing simulation of the design fitted to a PLD and programming and test- ing the PLD. The focus will be on the phases inside the dashed rectangle of Fig. 1 The portion of the design flow that is of interest in this laboratory is shown in more detail in Fig. 2. You will use three software tools during this laboratory: 1. Active-HDL: Compiler and Simulator 2. Synplify: Synthesizer 3. ispLEVER Classic: Place-and-route tool The first two tools you have used previously. The third tool, ispLEVER Classic, is a place-and- route tool that can fit a synthesized design to PLDs from technology vendor Lattice Semiconduc- tor. This Place-and-route tool takes the EDIF netlist from the synthesizer as its input. It generates Figure 1: Design flow for VHDL/PLD design methodology. Compile Test Bench Functional Simulation Select PLD Synthesize Logic Post-Synthesis Simulation Place and Route Logic to Fit PLD Timing Simulation Verify PLD's Operation Progam PLD Analyze Requirements Develop Specification Write VHDL Test Bench Write VHDL Design Description Compile Design Description
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a VHDL timing model of the logic fitted to the target PLD. Such a model represents both the functionality of the logic and its physical delays. Accordingly, during simulation, when the value of an input to the timing model is changed, the corresponding output(s) do not change immedi- ately. Instead, each output changes after an appropriate delay. This delay corresponds to the phys- ical delay caused by the primitive logic elements in the PLD through which the signal must pass from input to output. Design Tasks The VHDL testbench will have to be slightly modified later during this laboratory. The testbench will be modified twice. 1. So that the input stimuli change slowly enough to allow the output signals to be stable at their new values for a short period of time. 2. So that the timing simulation can easily be duplicated by applying electrical signals to a pro- grammed SPLD. Examine the VHDL testbench file from Laboratory 1. In the architecture body there is a process with the label tb . This process assigns values to signals a_tb and b_tb so that these signals Figure 2: The third portion of the complete VHDL/PLD design flow including timing simulation. Place and Route Synthesized Logic Timing Simulation Simulation Passed? 3
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lab02bs10 - ESE 382 Digital System Design Using VHDL and...

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