lab02as10 - ESE 382 Digital System Design Using VHDL and...

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1 ESE 382 Digital System Design Using VHDL and PLDs Spring 10, Ken Short Laboratory 2: VHDL/PLD Design Flow - Synthesis and Post Synthesis Simulation This laboratory is to be performed the week starting Feb. 7th. Prerequisite Reading 1. Sections 1.7 through 1.9 of the text. 2. ispGAL22V10C-10 Data Sheet. Purpose The purpose of this laboratory is to provide you with experience in how a VHDL design descrip- tion is synthesized and how the functionally of the synthesized logic is verified. The focus is on that portion of the VHDL/PLD design flow from the selection of a PLD to post synthesis simula- tion (Fig. 1, inside dashed rectangle). The half-adder VHDL design description from Laboratory 1 is to be synthesized and the VHDL netlist generated by the synthesizer is to be simulated. The purpose of this post synthesis simulation is to verify the functionality of the logic synthesized from the VHDL design description by the synthesizer. This post-synthesis simulation is often skipped, and the timing simulation used to verify both the functionality of the synthesized logic and its timing when mapped to the target PLD. The portion of the design flow that is of interest in this laboratory is shown in more detail in Fig. 2. The synthesizer tool used is Synplicity’s Synplify Pro. Synplify Pro is an CPLD and FPGA logic synthesis tool. Synplify Pro accepts design descriptions written in VHDL and creates netlists Figure 1: Design flow for VHDL/PLD design methodology. Compile Test Bench Functional Simulation Select PLD Synthesize Logic Post-Synthesis Simulation Place and Route Logic to Fit PLD Timing Simulation Verify PLD's Operation Progam PLD Analyze Requirements Develop Specification Write VHDL Test Bench Write VHDL Design Description Compile Design Description
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based on the selected target CPLD or FPGA. The netlists generated are: a VHDL netlist used for post synthesis simulation and an EDIF netlist used for programming the PLD. Design Tasks The first step in this sequence of phases is selection of a target PLD. This requires you to have a knowledge of the types of PLDs available, their architectures, capabilities, and performance. Since we have yet to cover PLD architectures in detail, the target PLD, an ispGAL22V10C-10, has been selected for you. Other than selection of a target PLD there are no other design aspects to this part of the design flow. Figure 2: The second portion of the detailed VHDL/PLD design flow including post-synthesis simulation. Select Target PLD Synthesize Design Description Post Synthesis Simulation Simulation Passed? 3 2 1 Synthesizer Simulator target PLD selection synthesized logic VHDL netlist Yes No compiled test bench file functionally tested design description Post Synthesis Simulation? Yes
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This note was uploaded on 08/30/2010 for the course ESE 382 taught by Professor Short during the Spring '10 term at SUNY Stony Brook.

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lab02as10 - ESE 382 Digital System Design Using VHDL and...

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