lab01s10 - 1 ESE 382 Digital System Design Using VHDL and...

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1 ESE 382 Digital System Design Using VHDL and PLDs Spring 10, Ken Short Laboratory 1: VHDL/PLD Design Flow - Compilation and Functional Simulation This laboratory is to be performed during your assigned laboratory section the week starting Jan. 31st. Prerequisite Reading 1. Sections 1.1 through 1.6 of Chapter 1 of VHDL for Engineers. 2. Design description and testbench source files (Listings 1.3.1 and 1.5.1 of Chapter 1) Purpose The purpose of this laboratory is for you to experience how a VHDL design description is com- piled and functionally simulated. The focus is on that portion of the VHDL/PLD design flow from writing the VHDL design description through functional simulation (Fig. 1, inside the dashed rectangle). It is assumed that requirements analysis and specification development have led to the need for a half-adder. The half-adder is to be designed and functionally simulated. The purpose of functional simulation is to verify the functionality of the VHDL design description. The simulator tool used is Aldec’s Active-HDL. The portion of the design flow that is of interest in this laboratory is shown in more detail in Fig. 2. After simulation of the half-adder is completed, you will create a second design and repeat the design flow. The second design is a half-subtractor. You will modify the half-adder design files to create the corresponding files for the half-subtractor. Figure 1: Design flow for VHDL/PLD design methodology. Compile Test Bench Functional Simulation Select PLD Synthesize Logic Post-Synthesis Simulation Place and Route Logic to Fit PLD Timing Simulation Verify PLD's Operation Progam PLD Analyze Requirements Develop Specification Write VHDL Test Bench Write VHDL Design Description Compile Design Description
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2 Figure 2: First portion of complete VHDL/PLD design flow includes functional simulation. Requirements Analysis Write (or Edit) VHDL Design Description Compile Design Description Functional Simulation Simulation Passed? Write (or Edit) VHDL Test Bench Compile Test Bench 2 1 1 Editor Editor Compiler Compiler Simulator VHDL design description source file compiled source file Yes No VHDL test bench source file compiled test bench file design phase tool legend functionally tested design description Develop Specification
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3 Design Tasks In future laboratory assignments you are required to carry out design tasks prior to your labora- tory session. Usually these tasks involve writing a VHDL design description and a VHDL test- bench and functionally simulating your design. However, in this laboratory the design files for the half-adder are provided for you. You will modify these files to create the half-subtractor. The half-adder design requires two design files (source files). The first file contains the VHDL design description of the half-adder. For Laboratory 1, you will create this file using Active- HDL’s Design Wizard. The second design file is a VHDL testbench file. It is the testbench file that is actually simulated.
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lab01s10 - 1 ESE 382 Digital System Design Using VHDL and...

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