LEC-15 - 15 Test Benches for Sequential Circuits...

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15 Test Benches for Sequential Circuits © Copyright 2003, 2006 Kenneth Shor 1 4/25/2010 © Copyright 2003, 2006 Kenneth Short 1 Testbenches for Sequential Circuits Kenneth Short 4/25/2010 © Copyright 2003, 2006 Kenneth Short 2 Comprehensive Verification ± Exhaustive functional verification is for sequential circuits can be extremely time consuming and often difficult or impossible ± Accordingly, for a sequential circuit something well short of exhaustive verification is usually necessitated ± The objective might be described as a comprehensive verification. A comprehensive verification is one that provides a high degree of confidence that a design is functionally correct. ± Producing a comprehensive verification raises the question of how well do the stimulus sequences you create cover the circumstances in which the circuit is expected to operate. ± Ultimately, the confidence you can have in a verification is limited by the thoroughness and appropriateness of the stimulus sequences used.
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15 Test Benches for Sequential Circuits © Copyright 2003, 2006 Kenneth Shor 2 4/25/2010 © Copyright 2003, 2006 Kenneth Short 3 Procedures in Sequential Test Benches ± Sequential circuit test benches require the generation of clock and reset signals in addition to input data stimulus signals. ± Procedures can be used to simplify the generation of stimulus waveform. ± Each procedure is written to create the waveforms required for a particular operation on the UUT. ± With generation of the waveforms for each operation encapsulated into procedures, verification is accomplished by calling procedures in an appropriate order. Procedures can also be used to monitor a UUT’s responses. 4/25/2010 © Copyright 2003, 2006 Kenneth Short 4 SA ADC Test Bench comp_out SAR DAC and Comparator Model soc eoc result comp_in analog_unknown (digital representation of analog input voltage) Test Bench 8 8
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15 Test Benches for Sequential Circuits © Copyright 2003, 2006 Kenneth Shor 3 4/25/2010 © Copyright 2003, 2006 Kenneth Short 5 SA ADC Test Bench Concurrent Statements ± The test bench architecture contains five concurrent statements: ² instantiation of SAR as UUT ² concurrent signal assignment to generate system clock ² concurrent signal assignment to generate system reset ² concurrent signal assignment to model DAC and comparator ² process to provide stimulus and monitor response 4/25/2010 © Copyright 2003, 2006 Kenneth Short 6 SA ADC Test Bench Code (Part 1)
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15 Test Benches for Sequential Circuits © Copyright 2003, 2006 Kenneth Shor 4 4/25/2010 © Copyright 2003, 2006 Kenneth Short 7 SA ADC Test Bench Code (Part 2) 4/25/2010 © Copyright 2003, 2006 Kenneth Short 8 SA ADC Test Bench Code (Part 3)
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15 Test Benches for Sequential Circuits © Copyright 2003, 2006 Kenneth Shor 5 4/25/2010 © Copyright 2003, 2006 Kenneth Short 9 SA ADC Test Bench Code (Part 4) 4/25/2010 © Copyright 2003, 2006 Kenneth Short 10 SA ADC Test Bench Waveforms
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15 Test Benches for Sequential Circuits © Copyright 2003, 2006 Kenneth Shor 6 4/25/2010 © Copyright 2003, 2006 Kenneth Short 11 Stimulus Sequence for a D Flip-Flop ±
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LEC-15 - 15 Test Benches for Sequential Circuits...

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