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LEC-12 - 12 Finite State Machines II Finite State Machines...

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12 Finite State Machines II 3/22/2010 © Copyright 2003, 2006 Kenneth L. Short 1 3/22/2010 © Copyright 2003, 2006 Kenneth L. Short 1 Finite State Machines II Prof. Ken Short 3/22/2010 © Copyright 2003, 2006 Kenneth L. Short 2 Inhibit Logic Example Usually, it is necessary to “double buffer” the output of a counter so that its value can be “read on the fly.” For example, if a 12 bit counter is to be read its contents may change during the time it takes to read them If the counter’s output were read directly, and the read operation occurred while the the counter were in the process of changing value, the value read would be incorrect. If a 12-bit counter’s output is to be read by a microprocessor with an 8-bit data bus, the 12-bit value must be read a byte at a time. This requires the microprocessor to execute two read bus cycles. This additional time to read the counter’s contents increases the likelihood of reading an incorrect value, if the counter’s output is not double buffered
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12 Finite State Machines II 3/22/2010 © Copyright 2003, 2006 Kenneth L. Short 2 3/22/2010 © Copyright 2003, 2006 Kenneth L. Short 3 Inhibit Logic Block Diagram Counter Buffer Register Mux Three- State Output Buffer Inhibit Logic FSM cnt_enble up D7-D0 clk rst_bar clk rst_bar clk rst_bar sel oe_bar inhibit 12 4 8 8 8 0 1 3/22/2010 © Copyright 2003, 2006 Kenneth L. Short 4 Inhibit Logic State Diagram reset_bar = '0' inhibit = '0' inhibit = '1' inhibit = '1' oe_bar = '1' oe_bar = '1' sel = '0' and oe_bar = '0' sel = '0' or (sel = '1' and oe_bar = '0') sel = '1' and oe_bar = '0' sel = '0' and oe_bar = '0' sel = '1' and oe_bar = '0' idle byte1 byte2
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12 Finite State Machines II 3/22/2010 © Copyright 2003, 2006 Kenneth L. Short 3 3/22/2010 © Copyright 2003, 2006 Kenneth L. Short 5 Inhibit Logic Code library ieee; use ieee.std_logic_1164. all ; entity inhibit_fsm is port ( rst_bar: in
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