LEC-10 - 10 Multibit Latches, Registers, and Counters...

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10 Multibit Latches, Registers, and Counters 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 1 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 1 Multibit Latches, Registers, and Counters Prof. Ken Short 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 2 Multibit Latches and Registers ± Two or more D latches with their clock inputs connected together form a multibit latch that stores multiple bits of data simultaneously, in response to a clock signal ± A similar structure using D flip-flops is called a register ± Using std_logic_vectors we can easily change a D latch into a multibit latch
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10 Multibit Latches, Registers, and Counters 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 2 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 3 Multibit Latch DQ CLK CLK CLK CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 CLK 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 4 Octal Latch Entity Declaration library ieee; use ieee.std_logic_1164. all ; entity octal_d_latch is port ( d: in std_logic_vector(7 downto 0); clk: in std_logic; set_bar: in std_logic; clear_bar: in std_logic; q: out std_logic_vector(7 downto 0) ); end octal_d_latch;
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10 Multibit Latches, Registers, and Counters 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 3 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 5 Octal Register Entity Declaration library ieee; use ieee.std_logic_1164. all ; entity ic74x574 is port ( d: in std_logic_vector(7 downto 0); clk: in std_logic; oe_bar: in std_logic; q: out std_logic_vector(7 downto 0) ); end ic74x574; 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 6 Octal Latch Architecture architecture behavioral of octal_d_latch is begin process (d, clk, set_bar, clear_bar) begin if set_bar = '0' then q <= x"ff"; elsif clear_bar = '0' then q <= x"00"; elsif clk='1' then q< =d; end if ; end process ; end behavioral;
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10 Multibit Latches, Registers, and Counters 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 4 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 7 Octal Register Architecture architecture behavioral of ic74x574 is signal q_int: std_logic_vector(7 downto 0); begin process (clk) begin if rising_edge(clk) then q_int <= d; end if ; end process ; q <= q_int when oe_bar = '0' else ( others => 'Z'); end behavioral; 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 8 Shift Register ± A shift register’s stored value is shifted one bit position (right or left) on each clock edge ± If the shift is to the right, all bits are shifted one position to the right, the input value is shifted into the leftmost position, and the original value in the rightmost position is shifted out ± A shift register that shifts in only one direction is easily implemented by connecting the Q output of one flip-flop to the D input of the next flip-flop
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10 Multibit Latches, Registers, and Counters 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 5 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 9 Shift Register Diagram DQ CLK CLK CLK CLK Q3 Q2 Q1 Q0 CLK D SOUT 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 10 Shift Register Declaration library ieee; use ieee.std_logic_1164. all ; entity shiftreg_rs is port (si, clr_bar, clk : in std_logic; qout : out std_logic_vector(3 downto 0)); end shiftreg_rs;
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10 Multibit Latches, Registers, and Counters 3/9/2009 © Copyright 2003, 2006 Kenneth L. Short 6 3/9/2009
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This note was uploaded on 08/30/2010 for the course ESE 382 taught by Professor Short during the Spring '10 term at SUNY Stony Brook.

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LEC-10 - 10 Multibit Latches, Registers, and Counters...

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